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| 型号： | WJLXT388LEB2 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14MM, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 30/80页 |
| 文件大小： | 1017K |
| 代理商： | WJLXT388LEB2 |
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Intel
LXT388 — Dual T1/E1/J1 Transceiver
36
Datasheet
The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed
operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS,
INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state
generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In
Motorola mode ACK Low signals valid information is on the data bus. During a write cycle a Low
signal acknowledges the acceptance of the write data.
In Intel mode RDY High signals to the controlling processor that the bus cycle can be completed.
While Low the microprocessor must insert wait states. This allows the LXT388 to interface with
wait-state capable micro controllers, independent of the processor bus speed. To activate this
function a reference clock is required on the MCLK pin.
There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the
reset register. Because of timing issues, the RDY line remains high after the first part of the cycle
is done, not signalling write cycle completion with another transition low. Add 2 microseconds of
delay to allow the reset cycle to completely initialize the device before proceeding.
An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to
the microprocessor.
The LXT388 has a 5 bit address bus and provides 18 user accessible 8-bit registers for
configuration, alarm monitoring and control of the chip.
2.12.1
Motorola Interface
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode
the falling edge of DS is used to latch the address information on the address bus. In multiplexed
operation the address on the multiplexed address data bus is latched into the device with the falling
edge of AS. In non-multiplexed mode, AS should be pulled High.
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference
for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/
W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising
edge on DS.
Both cycles require the CS signal to be Low and the Address pins to be actively driven by the
microprocessor. Note that CS and DS can be connected together in Motorola mode. In a write cycle
the data bus is driven by the microprocessor. In a read cycle the bus is driven by the LXT388.
Table 9.
Microprocessor Parallel Interface Selection
MUX
MOT/INTL
Operating Mode
Low
Motorola Non-Multiplexed
Low
High
Intel Non-Multiplexed
High
Low
Motorola Multiplexed
High
Intel Multiplexed
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