参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 13/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
24
4.0
DIAGNOSTIC FEATURES
4.1
Serial Remote Loopback
The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is
activated, the high-speed serial receive data from RXIP/N is presented at the high-speed transmit output
TXOP/N, and the high-speed recovered clock is selected and presented to the high-speed transmit clock input
of the Retimer. During serial remote loopback, the high-speed receive data (RXIP/N) is also converted to
parallel data and presented at the low-speed receive parallel interface RXDO[3:0]P/N. The recovered receive
clock is also divided by 4 and presented at the low-speed clock output RXPCLKOP/N to synchronize the
transfer of the 4-bit received parallel data. A simplified block diagram of serial remote loopback is shown in
Figure 16.
4.2
Parallel Remote Loopback
RLOOPP controls a more comprehensive version of remote loop-back that can also be used in conjunction
with the de-jitter PLL that is phase locked to the recovered receive clock. In this mode, the received signal is
processed by the CDR, and is sent through the serial to parallel converter. At this point, the 4-bit parallel data
and clock are looped back to the transmit FIFO. Concurrently, if receive clock jitter attenuation is also
employed, the received clock is divided down in frequency and presented to the input of the integrated phase/
frequency detector and is compared to the frequency of a VCXO that is connected to the VCXO_INP/N inputs.
With the LOOPTM_JA configured to use the recovered receive clock as the reference and VCXO_SEL
asserted, the VCXO is phase locked to the recovered receive clock. The de-jittered clock is then used to retime
the transmitter, resulting in the re-transmission of the de-jittered received data out of TXOP/N. A FIFO reset
using FIFO_RST should follow immediately after enabling/disabling parallel remote loopback. A simplified
block diagram of parallel remote loopback is shown in Figure 17.
FIGURE 16. SERIAL REMOTE LOOPBACK
FIGURE 17. PARALLEL REMOTE LOOPBACK
PISO
Re-Timer
LVPECL
Output Drivers
LVPECL
Input Drivers
CDR
SIPO
Rx Parallel Output
Tx Serial Output
Serial Remote Loopback
Rx Serial Input
FIFO
PISO
Re-Timer
LVPECL
Output Drivers
LVPECL
Input Drivers
CDR
SIPO
Rx Parallel Output
Tx Serial Output
Parallel Remote Loopback
Rx Serial Input
FIFO
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相关代理商/技术参数 |
参数描述 |
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| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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