参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 46/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
7
ALTFREQSEL
LVTTL,
LVCMOS
I
P1
Reference Clock Frequency Select
This pin is used to select the frequency of the REFCLKP/N
clock input to the CMU.
"Low" = 77.76 MHz (83.31 MHz for FEC)
"High" = 155.52 MHz (166.63 MHz for FEC)
This pin is provided with an internal pull-up.
VCXO_SEL
LVTTL,
LVCMOS
I
M6
De-Jitter VCXO Select Option
This pin selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N pin as a reference clock to the CMU.
"Low" = Normal REFCLKP/N reference clock
"High" = De-Jitter VCXO_INP/N reference clock
This pin is provided with an internal pull-down.
VCXO_LOCK
LVCMOS
O
N8
De-Jitter PLL Lock Detect
If the de-jitter PLL lock detect is enabled with pin P3 and the de-
jitter VCXO mode is selected by pin M6, this pin will assert
"High" when the PLL is locked.
"Low" = VCXO Out of Lock
"High" = VCXO Locked
VCXO_LOCKEN
LVTTL,
LVCMOS
I
P3
De-Jitter PLL Lock Detect Enable
This pin enables the VCXO_INP/N lock detect circuit and
VCXO_LOCK pin N8 to be active.
"Low" = VCXO Lock Detect Disabled
"High" = VCXO Lock Detect Enabled
This pin is provided with an internal pull-down.
CPOUT
-
O
P8
Charge Pump Output (for external VCXO)
The nominal output of the charge pump current is 250
A
LOOPBW
LVTTL,
LVCMOS
I
M7
CMU Loop Bandwidth Select
This pin is used to select the bandwidth of the clock multiplier
unit of the transmit path to a narrow or wide band. Use Wide
Band for clean reference signals and Narrow Band for noisy ref-
erences.
"Low" = Wide Band (4x)
"High" = Narrow Band (1x)
This pin is provided with an internal pull-down.
TXPCLKOP
TXPCLKON
LVDS
O
P10
P11
Transmit Parallel Clock Output
This 622.08 MHz clock can be used for the downstream device
to generate the TXDI[3:0]P/N data and TXPCLKIP/N clock
input. This enables the downstream device and the STS-48/
STM-16 transceiver to be in synchronization.
NOTE: The XRT91L80 can output a 666.51 MHz transmit clock
output for Forward Error Correction (FEC).
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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