参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 2/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
8
TXCLKO16P
TXCLKO16N
LVDS
O
N10
N11
Auxiliary Clock Output (155.52/166.63 MHz)
155.52/166.63 MHz auxiliary clock derived from CMU output.
This clock can also be used for the downstream device as a ref-
erence for generating the TXDI[3:0]P/N data and TXPCLKIP/N
clock input. This enables the downstream device and the STS-
48/STM-16 transceiver to be in synchronization. The output of
this pin is controlled by TXCLKO16DIS.
TXCLKO16DIS
LVTTL,
LVCMOS
I
M12
Auxiliary Clock Disable
This pin is used to control the activity of the auxiliary clock.
"Low" = TXCLKO16P/N Enabled
"High" = TXCLKO16P/N Disabled
This pin is provided with an internal pull-down.
LOCKDET_CMU
LVCMOS
O
N2
CMU Lock Detect
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU Out of Lock
"High" = CMU Locked
OVERFLOW
LVCMOS
O
M13
Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO_RST
LVTTL,
LVCMOS
I
N13
FIFO Control Reset
FIFO_RST should be held "High" for a minimum of 2 TXP-
CLKOP/N cycles after powering up and during manual FIFO
reset. After the FIFO_RST pin is returned "Low," it will take 8 to
10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an
interrupt indication that the FIFO has an overflow condition, this
pin is used to reset or flush out the FIFO.
"Low" = Normal Operation
"High" = Manual FIFO Reset
NOTE: To automatically reset the FIFO, see FIFO_AUTORST
pin.
This pin is provided with an internal pull-down.
FIFO_AUTORST
LVTTL,
LVCMOS
I
N12
Automatic FIFO Overflow Reset
If this pin is set "High", the STS-48/STM-16 transceiver will
automatically flush the FIFO upon an overflow condition. Upon
power-up, the FIFO should be manually reset by setting
FIFO_RST "High" for a minimum of 2 TXPCLKOP/N cycles.
"Low" = Manual FIFO reset required for Overflow Conditions
"High" = Automatically resets FIFO upon Overflow Detection
This pin is provided with an internal pull-down.
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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| VI-J51-MX-F4 | CONVERTER MOD DC/DC 12V 75W |
| V24B36M150BL | CONVERTER MOD DC/DC 36V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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