参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 32/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
35
TABLE 15: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
TABLE 16: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CONFIGURATION 1 CONTROL REGISTER (0X04H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
POLARITY
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W
0
D5
LOOPTM_JA
Loop Timing With Jitter Attenuation
The LOOPTM_JA bit must be set to "1" in order to select the recov-
ered receive clock as the reference source for the de-jitter PLL.
"0" = Disabled
"1" = Loop timing with de-jitter PLL Activated
R/W
0
D4
LOOPTM_
NOJA
Loop Timing With No Jitter Attenuation
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/32nd
of the high-speed recovered receive clock coming from the CDR.
"0" = Disabled
"1" = Loop timing Activated
R/W
0
D3
LOSDMUTE
Parallel Receive Data Output Mute Upon LOSD
If this bit is set to "1", the receive data output will automatically be
forced to a logic state of "0" when an LOSD condition occurs.
"0" = Disabled
"1" = Mute RXDO[3:0]P/N Data Upon LOSD Condition
R/W
0
D2
DISRD
Parallel Receive Data Output Disable
This bit is used to disable the RXDO[3:0]P/N parallel receive data
output bus asynchronously.
"0" = Normal Mode
"1" = Forces RXDO[3:0]P/N to a logic state "0"
R/W
0
D1
Reserved
Reserved - Set to 0
R/W
0
D0
VCXOLKEN
De-Jitter PLL Lock Detect Enable
This bit enables the VCXO_INP/N lock detect circuit to be active.
"0" = VCXO Lock Detect Disabled
"1" = VCXO Lock Detect Enabled
R/W
0
DIAGNOSTIC CONTROL REGISTER (0X05H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
Reserved
This Register Bit is Not Used
X
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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