参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 45/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
6
LOOPTM_JA
LVTTL,
LVCMOS
I
C6
Loop Timing Mode With Jitter Attenuation
The LOOPTM_JA pin must be set "High" in order to select the
recovered receive clock as the reference source for the de-jitter
PLL.
"Low" = Disabled
"High" = Loop timing with de-jitter PLL Activated
This pin is provided with an internal pull-down.
LOOPTM_NOJA
LVTTL,
LVCMOS
I
P2
Loop Timing Mode With No Jitter Attenuation
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/
32nd of the high-speed recovered receive clock coming from
the CDR.
"Low" = Disabled
"High" = Loop timing Activated
This pin is provided with an internal pull-down.
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
TXDI0P
TXDI0N
TXDI1P
TXDI1N
TXDI2P
TXDI2N
TXDI3P
TXDI3N
LVDS
I
H13
J13
K14
L14
K13
L13
M14
N14
Transmit Parallel Data Input
The 622.08 Mbps 4-bit parallel transmit data input should be
applied to the transmit parallel bus simultaneously to be sam-
pled at the rising edge of the TXPCLKIP/N input. The 4-bit par-
allel interface is multiplexed into the transmit serial output
interface MSB first (TXDI3P/N).
NOTE: The XRT91L80 can accept 666.51 Mbps 4-bit parallel
transmit data input for Forward Error Correction (FEC)
Applications.
TXPCLKIP
TXPCLKIN
LVDS
I
H14
J14
Transmit Parallel Clock Input
622.08 MHz clock input used to sample the 4-bit parallel trans-
mit data input TXDI[3:0]P/N.
NOTE: The XRT91L80 can accept a 666.51 MHz transmit clock
input for Forward Error Correction (FEC) Applications.
TXOP
TXON
CMLDIFF
O
K1
L1
Transmit Serial Data Output
The transmit serial data output stream is generated by multi-
plexing the 4-bit parallel transmit data input into a 2.488 Gbps
serial data output stream. In Forward Error Correction, the
transmit serial data output stream is 2.666 Gbps.
REFCLKP
REFCLKN
LVPECL
I
P6
N6
Reference Clock Input
This differential clock input reference is used for the transmit
clock multiplier unit (CMU) to provide the necessary high-speed
clock reference for this device. Pin ALTFREQSEL determines
the value used as the reference. See Pin ALTFREQSEL for
more details.
VCXO_INP
VCXO_INN
LVPECL
I
P4
N4
Voltage Controled Oscillator Input
This differential clock input is used for the transmit PLL jitter
attenuation. Pin ALTFREQSEL determines the value used as
the reference. See Pin ALTFREQSEL for more details.
HARDWARE COMMON CONTROL
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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