参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 31/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
34
D4
LOOPBW
CMU Loop Band Width Select
This bit is used to select the bandwidth of the clock multiplier unit
of the transmit path to a narrow or wide band. Use Wide Band for
clean reference signals and Narrow Band for noisy references.
"0" = Wide Band (4x)
"1" = Narrow Band (1x)
R/W
0
D3
VCXO_SEL
VCXO De-Jitter Select
This bit selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N as a reference clock.
"0" = Normal REFCLKP/N Mode
"1" = De-Jitter VCXO Mode
R/W
0
D2
TXCLKO16DIS
Auxiliary Clock Disable
This bit is used to control the activity of the auxiliary clock.
"0" = TXCLKO16P/N Enabled
"1" = TXCLKO16P/N Disabled
R/W
0
D1
FIFO_
AUTORST
Automatic FIFO Overflow Reset
If this bit is set to "1", the STS-48/STM-16 transceiver will automat-
ically flush the FIFO upon an overflow condition. Upon power-up,
the FIFO should be manually reset by setting FIFO_RST to "1" for
a minimum of 2 TXPCLKOP/N cycles.
"0" = Manual FIFO reset required for Overflow Conditions
"1" = Automatically resets FIFO upon Overflow Detection
R/W
0
D0
FIFO_RST
Manual FIFO Reset
FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N
cycles after powering up and during manual FIFO reset. After the
FIFO_RST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N
cycles for the FIFO to flush out. Upon an interrupt indication that
the FIFO has an overflow condition, this bit is used to reset or flush
out the FIFO.
"0" = Normal Operation
"1" = Manual FIFO Reset
NOTE: To automatically reset the FIFO, see the FIFO_AUTORST
bit.
R/W
0
TABLE 14: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
CONFIGURATION 0 CONTROL REGISTER (0X03H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
相关PDF资料 |
PDF描述 |
|---|---|
| V24B48M150BG2 | CONVERTER MOD DC/DC 48V 150W |
| VI-J52-MX-F1 | CONVERTER MOD DC/DC 15V 75W |
| V24B48M150BF2 | CONVERTER MOD DC/DC 48V 150W |
| VI-J51-MX-F4 | CONVERTER MOD DC/DC 12V 75W |
| V24B36M150BL | CONVERTER MOD DC/DC 36V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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