参数资料
型号: XRT91L80IB
厂商: Exar Corporation
文件页数: 41/46页
文件大小: 0K
描述: IC TXRX SONET/SDH 4BIT 196STBGA
产品变化通告: XRT91L80IB Obsolescence 6/Sept/2010
标准包装: 126
类型: 收发器
规程: SONET/SDH
电源电压: 3.3V
安装类型: 表面贴装
封装/外壳: 196-LFBGA
供应商设备封装: 196-STBGA(12x12)
包装: 托盘
xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
43
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 EXAR Corporation
Datasheet January 2007.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
P1.0.6
July 2005
1.Updated CML input swing characteristics table.
2.Updated CDR and CMU jitter performance parameters.
3.Updated Intrinsic Transmit and Receive Phase Noise performance plots.
4.Updated AC/DC electrical characteristics tables.
P1.1.0
July 2005
1.Revision E silicon: CMOS Digital 1.8V power pins P13 and P14 changed to 3.3V.
2.Revision E silicon: ALTFREQSEL default clock selection changed to 155.52 MHz.
P2.0.0
January 2006
1.Updated TXPCLKIP/N (tTXDI_SU) setup and (tTXDI_HD) hold time.
2.Added RXPCLKOP/N (tRX_INV) invalid and (tRX_DEL) data typical delay time.
3.Added RXPCLKOP/N (RXDUTY) typical duty cycle.
P.2.0.1
January 2007
Changed the Max values of tRX_IN and tRX_DEL in Table 5 from 200 to 300 ps
Changed the Min values of tTXDI_SU and tTXDI_HD in Table 6 from 200 to 300 ps
Changed the Max value of TXDUTY Table 7 from 55 to 58 ps
Enhanced Figure 16, Figure 17 and Figure 18.
Added Figure 21 and Figure 23
Changed TOLJIT Min value from 0.4 UI to 0.35 UI in Table 3
Changed the VISINGLE Max value from 600 mV to 500 mV in the Common Mode
Logic Signal DC Electrical Characteristics
Changed IDD_1.8 and IDD_IO in the Power and Current DC Electrical Characteristics
table
Changed ILEAK_PU and ILEAK_PD in the LVTTL/LVCMOS Signal DC Electrical Char-
acteristics
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
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