参数资料
| 型号： | XRT91L80IB |
| 厂商： | Exar Corporation |
| 文件页数： | 9/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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xr
XRT91L80
REV. 1.0.0
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
15
2.2
Receive Clock and Data Recovery
The clock and data recovery unit accepts the high speed NRZ serial data from the differential CML receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery utilizes the
REFCLKP/N to train and monitor its clock recovery PLL. Initially upon startup, the PLL locks to the local
reference clock within ±500 ppm. Once this is achieved, the PLL then attempts to lock onto the incoming
receive data stream. Whenever the recovered clock frequency deviates from the local reference clock
frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto the
local reference clock. When this condition occurs the PLL will declare Loss of Lock and the LOCKDET_CDR
signal will be pulled "Low." Whenever a Loss of Lock/Loss of Signal Detection (LOSD) event occurs, the CDR
will continue to supply a receive clock (based on the local reference clock) to the upstream framer device. A
Loss of Lock condition will also be declared when the external SDEXT becomes inactive. When the SDEXT is
de-asserted by the optical module and LOSDMUTE is enabled, receive parallel data output will be forced to a
logic zero state for the entire duration that a LOSD condition is detected. This acts as a receive data mute upon
LOSD function to prevent random noise from being misinterpreted as valid incoming data. When SDEXT
becomes active and the recovered clock is determined to be within ±500 ppm accuracy with respect to the
local reference source, the clock recovery PLL will switch and lock back onto the incoming receive data stream
and the lock detect output (LOCKDET_CDR) will go active. Table 3 specifies the Clock and Data Recovery Unit
performance characteristics.
TABLE 3: CLOCK AND DATA RECOVERY UNIT PERFORMANCE
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1Required to meet SONET output frequency stability requirements.
2.3
External Signal Detection
XRT91L80 supports external Signal Detection (SDEXT). The external Signal Detect function is supported by
the SDEXT input. This input is coming from the optical module through an output usually called “SD” or “FLAG”
which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the
polarity of this signal can be either active "Low" or active "High." The SDEXT and POLARITY inputs are
Exclusive OR’ed to generate the external LOSDET signal, internal Loss of Signal Detect (LOSD) declaration
and Mute upon LOSD control signal. Whenever an external SD is absent, the XRT91L80 will automatically
output a high level signal on the LOSDET output pin as well as update the control registers whenever the host
mode serial microprocessor interface feature is active. If LOSDMUTE is enabled, it will force the receive
parallel data output to a logic state "0" for the entire duration that a LOSD condition is declared. This acts as a
receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming
data. Table 4 specifies SDEXT declaration polarity settings.
NAME
PARAMETER
MIN
TYP
MAX
UNITS
REFDUTY
Reference clock duty cycle
45
55
%
REFTOL
Reference clock frequency tolerance1
-20
+20
ppm
OCLKJIT
Clock output jitter generation with 77.76 MHz reference clock
3.5
5.0
mUIrms
OCLKJIT
Clock output jitter generation with 155.52 MHz reference clock
3.7
5.0
mUIrms
TOLJIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0..35
0.5
UI
OCLKFREQ
Frequency output
2.488
2.667
GHz
OCLKDUTY
Clock output duty cycle
45
55
%
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L80IB-F | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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