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参数资料
| 型号： | YF80532KC0412M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 22/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0412M |
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118
Datasheet
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all processor system bus
agents and if used, must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal
any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration (see Section 6.1)
and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity
and bus request arbitration state machines. The bus agents do not reset their IOQ
and transaction tracking state machines upon observation of BINIT# assertion.
Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for
the system bus and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system
bus agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BPM[5:0]#
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all Intel Xeon processor MP on the 0.13
micron process processor system bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is
used by debug tools to request debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
These signals do not have on-die termination and must be terminated at the
end agent. See the ITP Debug Port Design Guide for more information.
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
system bus. It must connect the appropriate pins of all processor system bus
agents. Observing BPRI# active (as asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such requests are part of an ongoing
locked operation. The priority agent keeps BPRI# asserted until all of its requests
are completed, then releases the bus by deasserting BPRI#.
Table 52. Signal Definitions (Sheet 2 of 10)
Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| YF80532KC0371M | 1900 MHz, MICROPROCESSOR, CPGA603 |
| YG101-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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