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参数资料
| 型号： | YF80532KC0412M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 41/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0412M |
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Datasheet
19
Electrical Specifications
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
2.5.1
Mixing Processors
Intel only supports multi-processor combinations that operate with the same system bus frequency,
core frequency, VID settings, and cache sizes. Mixing processors operating at different internal
clock frequencies is not supported and will not be validated by Intel. Not all operating systems can
support multiple processors with mixed frequencies. Intel does not support or validate operation of
processors with different cache sizes. Mixing processors of different steppings but the same model
(as per CPUID instruction) is supported. Details on CPUID are provided in the Intel Processor
Identification and the CPUID Instruction application note.
Unlike previous Intel Xeon processors, the Intel Xeon processor with 512-KB L2 cache and the
Low Voltage Intel Xeon processor do not sample the pins IGNNE, LINT0, LINT1, and A20M# to
establish the core to system bus ratio. Rather, the processor runs at its tested frequency at initial
power-on. If the processor needs to run at a lower core frequency, as must be done when a higher
speed processor is added to a system that contains a lower frequency processor, the system BIOS
writes a value in the MSR_EBC_FREQ_GOAL (Ratio Configuration Register), and asserts a
system reset to effect the change in the core to system bus ratio. On previous platforms, the second
reset has not been required, so the impact of this second reset needs to be comprehended by the
system designer.
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0 dB
-28 dB
-34 dB
0.2 dB
forbidden
zone
-0.5 dB
forbidden
zone
1 MHz
66 MHz
fcore
fpeak
1 Hz
DC
passband
high frequency
band
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