36
Datasheet
Electrical Specifications
5. Rise time is measured from (VIL_MAX - 0.15 V) to (VIH_MIN + 0.15 V). Fall time is measured from (0.9 *
SM_VCC) to (VIL_MAX - 0.15V). DC parameters are specified in Table 12. 6. Following a write transaction, an internal device write cycle time of 10ms must be allowed before starting the
next transaction.
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables,
Table 14 through
Note:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core (pads).
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated
strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All
AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads).
4. All AC Timing for the TAP signals are referenced to the TCK signal at 0.5 * Vcc at the
processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * Vcc at the
processor core (pads).
5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC
at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc) are referenced
at VIL_MAX or VIL_MIN at the processor pins.
Figure 4. Electrical Test Circuit
Vtt
Rload = 50 ohms
C = 1.2pF
L = 2.4nH
AC Timings
specified at pad.
Zo = 50 ohms, d=420mils, So=169ps/in