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参数资料
| 型号： | YF80532KC0412M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 39/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0412M |
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Datasheet
17
Electrical Specifications
operate. If lower speeds are desired, the appropriate ratio can be set with software using
MSR_EBC_FREQ_GOAL to produce a lower operating speed. For details of operation at core
frequencies lower than the maximum rated processor speed.
Clock multiplying within the processor is provided by the internal PLL, which requires a constant
frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC
specifications must be met while also meeting signal integrity requirements as outlined in
Section 3. The Intel Xeon processor MP on the 0.13 micron process processor utilizes a differential
clock. Details regarding BCLK[1:0] driver specifications are provided in the CK00 Clock
Synthesizer/Driver Design Guidelines. Table 2 contains Intel Xeon processor MP on the 0.13
micron process processor bus fraction ratios and their corresponding core frequencies.
NOTES:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. Platforms should support a 400 MHz system bus.
2.4.1
Bus Clock
The system bus frequency is set to the maximum supported by the individual processor. BSEL[1:0]
are outputs used to select the system bus frequency. Table 3 defines the possible combinations of
the signals and the frequency associated with each combination. The frequency is determined by
the processor(s), chipset, and clock synthesizer. All system bus agents must operate at the same
frequency. Individual processors will only operate at their specified system bus clock frequency.
The Intel Xeon processor with a 400 MHz system bus is designed to run on a baseboard with a
100 MHz bus clock. On these baseboards, BSEL[1:0] are both considered ‘reserved’ at the
processor socket. No change is required for operation with Intel Xeon processor MP on the 0.13
micron process processors. Operation will default to 100 MHz.
See the appropriate platform design guide for further details.
Table 2. Core Frequency to System Bus Multiplier Configuration
Core Frequency to System Bus
Multiplier Configuration
Core Frequency 100 MHz BCLK
Notes1,2,3
1/12
1.20 GHz
1/13
1.30 GHz
1/14
1.40 GHz
1/15
1.50 GHz
1/16
1.60 GHz
1/17
1.70 GHz
1/18
1.80 GHz
1/19
1.90 GHz
1/20
2 GHz
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