参数资料
型号: ZL50114GAG
厂商: XILINX INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-552
文件页数: 31/113页
文件大小: 2004K
代理商: ZL50114GAG
ZL50110/11/12/14
Data Sheet
24
Zarlink Semiconductor Inc.
3.0
External Interface Description
The following key applies to all tables:
3.1
TDM Interface
All TDM Interface signals are 5 V tolerant.
All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be
safely left unconnected if not used.
3.1.1
ZL50111 Variant TDM Stream Connection
I
Input
OOutput
D
Internal 100 k
Ω pull-down resistor present
U
Internal 100 k
Ω pull-up resistor present
T
Tri-state Output
Signal
I/O
Package Balls
Description
TDM_STi[31:0]
I D
[31]
D26
[15]
B16
[30]
E25
[14]
D14
[29]
D25
[13]
B14
[28]
C26
[12]
D13
[27]
C25
[11]
C12
[26]
E20
[10]
B11
[25]
F18
[9]
C11
[24]
B25
[8]
D11
[23]
E18
[7]
A8
[22]
C22
[6]
A6
[21]
A23
[5]
D8
[20]
A21
[4]
B5
[19]
C18
[3]
C5
[18]
A19
[2]
B3
[17]
B17
[1]
E9
[16]
C16
[0]
D5
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[31:0]
H.110:
TDM_D[31:0]
H-MVIP: TDM_HDS[31:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [7:0] are used, with 128 channels
per stream. Streams [7:0] are used for J2,
and streams [1:0] are used for T3 and E3.
Table 2 - TDM Interface ZL50111 Stream Pin Definition
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ZL50115 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors
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