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参数资料
| 型号： | ZL50114GAG |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 73/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG |
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ZL50110/11/12/14
Data Sheet
62
Zarlink Semiconductor Inc.
Contexts in the TDM to PKT direction are placed in the UPDATE state when they are opened, pending the local
clock source generation. If there is no local clock source to generate packets, the context will remain in the
UPDATE state and cannot be closed. ZL5011x Design Manual section “13.1 Understanding forceDelete” describes
the procedure to close transmit contexts in the UPDATE state.
When the payload has been assembled it is written into the centrally managed memory, and a task message is
passed to the Task Manager.
5.4.1
Structured Payload Operation
In structured mode a context may contain any number of 64 kbps channels. These channels need not be
contiguous and they may be selected from any input stream.
Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth
utilisation. Modifications to the context are synchronised with the start of a new packet.
The fixed header at the start of each packet is added by the Packet Transmit block. This consists of up to 64 bytes,
containing the Ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see
section below). The header is entirely user programmable, enabling the use of any protocol.
The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet
standard minimum packet size. Where this is likely to be the case, the header or data must be padded (as shown in
Figure 15 and Figure 17) to ensure the packet is large enough. This padding is added by the ZL50110/11/12/14 for
most applications.
Figure 15 - ZL50110/11/12/14 Packet Format - Structured Mode
In applications where large payloads are being used, the payload size must be chosen such that the overall packet
size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). Figure 15
Channel 1
Channel 2
Channel x
Data for TDM Frame 1
Header
Ethernet FCS
TDM Payload
(constructed by Payload Assembler)
Data for TDM Frame n
Channel 1
Channel 2
Channel x
Data for TDM Frame 2
Channel 1
Channel 2
Channel x
Ethernet Header
Network Layers
(added by Packet Transmit)
Upper layers
(added by Protocol Engine)
e.g. IPv4, IPv6, MPLS
e.g. UDP, L2TP, RTP,
CESoPSN, SAToP
may include VLAN tagging
Static Padding
(if required to meet minimum payload size)
may also be placed in the
packet header
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PDF描述 |
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| ZL50232GD | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| ZL50233/GDG | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| ZL50408GDC | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| ZL50408GDG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| ZL50418GKG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50114GAG2 | 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 552BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 552PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 552PBGA |
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
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