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参数资料
| 型号： | ZL50114GAG |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 77/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG |
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ZL50110/11/12/14
Data Sheet
66
Zarlink Semiconductor Inc.
Figure 18 - Differential Clock Recovery
For in-band differential algorithm, the ZL50110/11/12/14 inserts the timestamp after the packet payload is fully
assembled. The insertion-time may be in error by up to 8 UI of the nominal service clock (for example 8 * 488 ns of
an E1 interface).This variable error will occur in unstructured mode only, and result in degradation of performance
at the remote end, which uses the timestamps to recover a clock frequency. This error is most likely to occur when
there are many asynchronous (PDH) clocks that are close in frequency. In this case it is recommended to used the
Zarlink proprietary in-band differential.
Also, for in-band differential clock recovery, the frequency must be the same as the common clock frequency.
6.2
Adaptive Clock Recovery
For applications where there is no common reference clock between provider edge units, an adaptive clock
recovery technique is provided. The Adaptive clock recovery solution provided in the Zarlink CESoP products is a
combination hardware and software. The chip contains a DCO per TDM port in unstructured mode, that enables the
recovery of up to 32 independent clocks. The timing algorithm resides in the API and runs out of the host processor.
The basic information is transmitted using timestamps. Current CES standards allow for using of timestamps.
Timestamps may be implied by the value of the sequence numbers, or it can be formatted as RTP timestamps.
When a packet containing TDM data is sent, an RTP timestamp and/or sequence number is placed into the packet
header. On arrival at the receiving device, the arrival time is noted in the form of a local timestamp, driven by the
output clock of the TDM port it is destined for.
The recovered clock at the egress point of the ZL50110/11/12/14 is based on non-linear filtering of the timestamps
that are carried in the CESoP packets. The performance of the clock recovery is greatly improved by applying these
non-liner filtering techniques. The adaptive clock recovery performance is dependent on the network configuration
and operation, if the loading of the network is constrained, then the wander of the recovered clock will not exceed
the specified limits.
LIU
ZL5011x
source
node
ZL5011x
destination
node
Timestamp
generation
Timestamp
extraction
Host CPU
Timing
recovery
DCO
Data
Source
Clock
Data
Dest'n
Clock
Packets
PRS
clock
Network
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| ZL50408GDC | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50114GAG2 | 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 552BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 552PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 552PBGA |
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
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