参数资料
型号: ZL50114GAG
厂商: XILINX INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-552
文件页数: 47/113页
文件大小: 2004K
代理商: ZL50114GAG
ZL50110/11/12/14
Data Sheet
39
Zarlink Semiconductor Inc.
M1_RXD[7:0]
I U
[7]
M25
[3]
N25
[6]
P26
[2]
N24
[5]
M24
[1]
R26
[4]
P25
[0]
T26
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_RXCLK (GMII/MII) or the rising
edges of M1_RBC0 and M1_RBC1 (TBI).
M1_RXDV /
M1_RXD[8]
I D
M26
GMII/MII - M1_RXDV
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
TBI - M1_RXD[8]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
M1_RXER /
M1_RXD[9]
I D
L21
GMII/MII - M1_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M1_RXD[9]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
M1_CRS /
M1_Signal_Detect
I D
L23
GMII/MII - M1_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active high.
TBI - M1_Signal Detect
Similar function to M1_CRS.
M1_TXCLK
I U
L22
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII
100 Mbps
M1_TXD[7:0]
O
[7]
R24
[3]
R22
[6]
P22
[2]
P21
[5]
R23
[1]
T22
[4]
T23
[0]
R21
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_TXCLK (MII) or the rising edge
of M1_GTXCLK (GMII/TBI).
M1_TXEN /
M1_TXD[8]
O
P23
GMII/MII - M1_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M1_TXD[8]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
MII Port 1
Signal
I/O
Package Balls
Description
Table 11 - MII Port 1 Interface Package Ball Definition (continued)
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