参数资料
型号: ZL50114GAG
厂商: XILINX INC
元件分类: 通信及网络
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA552
封装: 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-552
文件页数: 56/113页
文件大小: 2004K
代理商: ZL50114GAG
ZL50110/11/12/14
Data Sheet
47
Zarlink Semiconductor Inc.
CPU_TA
OT
AB14
CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the
ZL50110/11/12/14 is ready to accept
data from the host. The data is written
on the rising edge of CPU_CLK
following the assertion. Returns to
tri-state from the negative clock edge of
CPU_CLK following the de-assertion of
CPU_CS.
CPU_DREQ0
OT
AC15
CPU DMA 0 Request Output Active low
synchronous to CPU_CLK rising edge.
Asserted by ZL50110/11/12/14 to
request the host initiates a DMA write.
Only used for DMA transfers, not for
normal register access.
CPU_DREQ1
OT
AE16
CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by
ZL50110/11/12/14 to indicate packet
data is ready for transmission to the
CPU, and request the host initiates a
DMA read. Only used for DMA transfers,
not for normal register access.
CPU_IREQO
O
AF17
CPU Interrupt 0 Request (Active Low)
CPU_IREQ1
O
AD16
CPU Interrupt 1 Request (Active Low)
Signal
I/O
Package Balls
Description
Table 15 - CPU Interface Package Ball Definition (continued)
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相关代理商/技术参数
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