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参数资料
| 型号： | ZL50114GAG |
| 厂商： | XILINX INC |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA552 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034, BGA-552 |
| 文件页数： | 44/113页 |
| 文件大小： | 2004K |
| 代理商： | ZL50114GAG |
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ZL50110/11/12/14
Data Sheet
36
Zarlink Semiconductor Inc.
M0_COL
I D
Y25
GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M0_RXD[7:0]
I U
[7]
W25
[3]
W26
[6]
W24
[2]
U22
[5]
U23
[1]
Y26
[4]
V24
[0]
AA26
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
M0_RXDV /
M0_RXD[8]
I D
V25
GMII/MII - M0_RXDV
Receive Data Valid. Active high. This
signal is clocked on the rising edge of
M0_RXCLK. It is asserted when valid data
is on the M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_RXER /
M0_RXD[9]
I D
V26
GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used
in conjunction with M0_RXD when
M0_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_CRS /
M0_Signal_Detect
I D
U25
GMII/MII - M0_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
TBI - M0_Signal Detect
Similar function to M0_CRS.
M0_TXCLK
I U
U24
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII
100 Mbps
M0_TXD[7:0]
O
[7]
V21
[3]
AA23
[6]
W23
[2]
W21
[5]
W22
[1]
Y22
[4]
Y23
[0]
AA22
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_TXCLK (MII) or the rising edge
of M0_GTXCLK (GMII/TBI).
MII Port 0
Signal
I/O
Package Balls
Description
Table 10 - MII Port 0 Interface Package Ball Definition (continued)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50114GAG2 | 制造商:Microsemi Corporation 功能描述:CESOP PROCESSOR 552BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CESOP PROCESSOR 128CH 552PBGA 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 128CH 552PBGA |
| ZL50115 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
| ZL50115GAG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 324BGA - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50115GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 1 TDM + 1 ETHERNET - Trays 制造商:Microsemi Corporation 功能描述:IC CESOP PROCESSOR 32CH 324PBGA |
| ZL50116 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:32, 64 and 128 Channel CESoP Processors |
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