参数资料
型号: AD6654BBC
厂商: Analog Devices Inc
文件页数: 11/88页
文件大小: 0K
描述: IC ADC 14BIT W/6CH RSP 256CSPBGA
标准包装: 1
位数: 14
采样率(每秒): 92.16M
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 2.5W
电压电源: 模拟和数字
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 256-BGA,CSPBGA
供应商设备封装: 256-CSPBGA(17x17)
包装: 托盘
输入数目和类型: 1 个差分,单极
AD6654
Rev. 0 | Page 19 of 88
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12
34
5
6
78
9
10
11
12
13
14
15
16
A
DGND
D14
D12
CPUCLK
(SCLK)
PC3
PCCH1
PA12
PAIQ
PAGAIN
PB6
CLK
OVR
AVDD
AGND
A
B
D7
CHIPID3
CHIPID2
DS
(RD,
SRFS)
PC5
PA5
PA15
PAACK
PB2
PB4
EXPC2
DNC
AVDD
AGND
B
C
CHIPID0
MODE
DTACK
(RDY,
SDO)
R/W
(WR,
STFS)
PC0
PA3
PA9
PACH2
PB9
EXPC1
AVDD
AGND
C
D
EXT_
FILTER
MSB_
FIRST
CS
(SCS)
PC6
PC2
PA1
PA7
PACH0
PB15
EXPC0
DRVDD
AVDD
AGND
D
E
CHIPID1
IRP
VDDIO
VDD
CORE
PCACK
VDD
CORE
VDD
CORE
VDD
CORE
VDDIO
DRVDD
AVDD
AGND
E
F
SMODE
D13
D15
RESET
D1
VDD
CORE
VDD
CORE
VDD
CORE
VDDIO
DRVDD
AVDD
AGND
C2
F
G
DGND
D8
D9
D2
D5
DGND
DRVDD
AVDD
AGND
G
H
D3
D11
D4
D10
A6
DGND
DRVDD
AVDD
AGND
C1
H
J
DGND
D6
D0
A7
A1
DGND
DRVDD
AVDD
AGND
J
K
A5
A0 (SDI)
A2
PC8
DGND
DRVDD
AVDD
AGND
K
L
A3
PC11
PC15
PC10
VDDIO
VDD
CORE
VDD
CORE
VDD
CORE
DRVDD
AVDD
AGND
AIN
L
M
PC14
PC13
PC9
PC7
PCCH0
VDDIO
VDD
CORE
VDD
CORE
VDD
CORE
DRVDD
AVDD
AGND
AIN+
M
N
PC1
PC4
PA13
PA8
PA0
PAREQ
PB1
PBREQ
DGND
DRVDD
AVDD
AGND
N
P
PCIQ
PCREQ
PA14
PA10
PB10
PB7
PB8
PBCH1
PBACK
PBCH0
SYNC2
DRVDD
AVDD
AGND
P
R
PCCH2
PCGAIN
PA6
PA2
PACH1
PB13
PB11
PBCH2
PB14
PBGAIN
SYNC1
DRVDD
AGND
ENC
R
T
DGND
PA11
PA4
PCLK
PB5
PB12
PBIQ
DGND
DNC
SYNC0
SYNC3
DR
AGND
VREF
AGND
ENC+
T
12
34
5
6
78
9
10
11
12
13
14
15
16
A4
PC12
PB3
PB0
VDDIO
05156-018
DNC = DO NOT CONNECT
Figure 18. 256 BGA Configuration (Top View)
Table 11. Pin Function Descriptions
Name
Type
Pin Number
Function
POWER SUPPLY
AVDD
Power
See
5 V Analog ADC Core Supply.
DRVDD
Power
See
3.3 V ADC Output Driver Supply.
VDDCORE
Power
See
1.8 V Digital DDC Core Supply.
VDDIO
Power
See
3.3 V Digital DDC I/O Supply.
DGND
Ground
See
Digital Core and I/O Ground.
AGND
Ground
See
Analog ADC Ground.
ADC INPUTS
AIN+
Input
M16
Differential Analog Input.
AIN
Input
L16
Differential Analog Input.
ENC+
Input
T16
Differential Encode Input. Conversion initiated on rising edge.
ENC
Input
R16
Differential Encode Input.
ADC OUTPUTS
DR
Output
T12
Data Ready. Inverted and delayed representation of ENC+ used for driving the DDC CLK
input.
OVR
Output
A12
Overange Bit. A logic high indicates analog input exceeds ±FS.
VREF
Output
T14
2.4 V Fixed Internal Voltage Reference. Bypass to AGND with 0.1 F chip capacitor.
C1
Output
H16
Compensation Pin for ADC Voltage Reference. Bypass to AGND with 0.1 F chip capacitor.
C2
Output
F16
Compensation Pin for ADC Voltage Reference. Bypass to AGND with 0.1 F chip capacitor.
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