参数资料
| 型号： | AD6654BBC |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/88页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 92.16M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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AD6654
Rev. 0 | Page 4 of 88
GENERAL DESCRIPTION
The AD6654 is a mixed-signal IF-to-baseband receiver
consisting of a 14-bit, 92.16 MSPS analog-to-digital converter
(ADC) and a 4-/6-channel, multimode digital down-converter
(DDC) capable of processing up to six WCDMA (wideband
code division multiple access) channels. The AD6654 has been
optimized for the demanding filtering requirements of wide-
band standards such as CDMA2000, UMTS, and TD-SCDMA,
but is flexible enough to support wider standards such as
WiMAX. It is typically used as part of a radio system that
digitally demodulates and filters IF sampled signals.
The ADC stage features a high performance track-and-hold
input amplifier (T/H), integrated voltage reference, and 14-bit
sampling resolution. Input signals up to 200 MHz can be
accurately digitized at encode rates up to 92.16 MSPS. The ADC
data outputs are internally routed directly into the DDC inputs,
where down-conversion, decimation and digital filtering are
performed. An overrange (OVR) output bit provides indication
of excessive ADC input levels. An ADC data-ready (DR) output
bit provides a synchronized clock for the integrated DDC.
Data from the ADC is evaluated for peak or mean power in the
input stage of the DDC, and the result is available to the user via
control register access. The DDC input stage also outputs 3-bit
level-indicator data (EXP) bits that can be used to control the
gain of the external DVGA in 6 dB steps (up to 48 dB) to
optimize signal amplitude into the ADC input.
The DDC stage has the following signal processing stages: six
WCDMA-ready channels, each consisting of a frequency
translator, a fifth-order cascaded integrated comb filter, two sets
of cascaded fixed coefficient FIR and half-band filters, three
cascaded programmable sum of product FIR filters, an
interpolating half-band filter (IHB), and a digital automatic
gain control (AGC) block. Multiple modes are supported for
clocking data out of the chip. Programming is accomplished via
serial or microport interfaces.
Frequency translation is accomplished with a 32-bit complex
numerically controlled oscillator (NCO). The NCO has greater
than 110 dBc SDFR. This stage translates a real input signal
from an intermediate frequency (IF) to a baseband complex
digital output. Phase and amplitude dither can be enabled on-
chip to improve spurious performance of the NCO. A 16-bit
phase-offset word is available to create a known phase relation-
ship between multiple AD6654 chips or channels. The NCO can
also be bypassed.
Following frequency translation is a fifth-order CIC filter with a
programmable decimation between 1 and 32. This filter is used
to efficiently lower the sample rate, while providing sufficient
alias rejection at frequencies at higher offsets from the signal
of interest.
Following the CIC5 are two sets of filters. Each filter set
includes a nondecimating FIR filter and a decimate-by-2 half-
band filter. The FIR1 filter provides about 30 dB of rejection,
while the HB1 provides about 77 dB of rejection. These two sets
of filters can be used together to achieve a 107 dB stop-band
alias rejection, or they can be individually bypassed to save
power.
The FIR2 filter provides about 30 dB of rejection, while the HB2
filter provides about 65 dB of rejection. The filters can be used
together to achieve more than 95 dB stop-band alias rejection,
or they can be individually bypassed to save power. FIR1 and
HB1 filters can run at the maximum ADC data port rate. In
contrast, FIR2 and HB2 can run with a maximum input rate of
75 MSPS (input rate to FIR2 and HB2 filters).
The programmable filtering is divided into three cascaded RAM
coefficient filters (RCFs) for flexible and power-efficient
filtering. The first filter in the cascade is the MRCF, consisting
of a programmable nondecimating FIR. It is followed by
programmable FIR filters (DRCF) with decimation from 1 to
16. They can be used either together to provide high rejection
filters, or independently to save power. The maximum input
rate to the MRCF is one-fourth the PLL clock rate.
The CRCF (Channel RCF) is the last programmable FIR filter
with programmable decimation from 1 to 16. It is typically used
to meet the spectral mask requirements for the air standard of
interest. This could be an RRC, antialiasing filter or any other
real data filter. Decimation in preceding blocks is used to keep
the input rate of this stage as low as possible for the best filter
performance.
The last filter stage in the chain is an interpolate-by-2 half-band
filter, which is used to up-sample the CRCF output to produce
higher output oversampling. Signal rejection requirements for
this stage are relaxed, because preceding filters have already
filtered the blockers and adjacent carriers.
The DDC input port of the AD6654 has its own clock input
used for latching the input data, as well as for providing the
input for an onboard PLL clock multiplier. The output of the
PLL clock is used for processing all filters and processing blocks
beyond the data router following CIC filter. The PLL clock can
be programmed to have a maximum clock rate of 200 MHz.
Typically, the DDC input clock is driven directly from the
integrated ADC’s data-ready (DR) output to ensure proper
synchronization.
A data routing block is used to distribute data from the CICs to
the various channel filters. This block allows multiple back-end
filter chains to work together to process high bandwidth signals
or to make even sharper filter transitions than a single channel
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相关代理商/技术参数 |
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|---|---|
| AD6654BBCZ | 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654CBC | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
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