参数资料
| 型号： | AD6654BBC |
| 厂商： | Analog Devices Inc |
| 文件页数： | 76/88页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 92.16M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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AD6654
Rev. 0 | Page 78 of 88
<2:1>: Monitor Function Select Bits. Table 32 describes the
function of these bits.
Table 32. Monitor Function Select Bits
Monitor Function Select
Function Enabled
00
Peak detect mode
01
Mean power monitor mode
10
Threshold crossing mode
11
Invalid selection
<0>: Monitor Enable Bit. When this bit is set, the power
monitoring function is enabled and operates as selected by Bit 2
to Bit 1 of the signal monitor register. When this bit is cleared,
the power monitoring function is disabled and the signal
monitor register bits <2:1> are don’t care bits. These bits default
to 0 on power-up.
CHANNEL REGISTER MAP
Channel control registers are common to all six channels, and
access to specific channels is determined by the channel I/O
access register (Address 0x02).
NCO Control <15:0>
These bits control the NCO operation.
<8:7>: NCO Sync Start Select Bits. These bits determine which
SYNC input pin is used by this channel for a start synchroniza-
tion operation. Table 33 describes the selection.
Table 33. Sync Start Select Bits
NCO Control <8:7>
SYNC Pin Used for Start
Synchronization
00
SYNC0
01
SYNC1
10
SYNC2
11
SYNC3
<6:5>: NCO Sync Hop Select Bits. These bits determine which
SYNC input pin is used by this channel for a hop synchroniza-
tion operation. Table 34 describes the selection.
Table 34. Sync Hop Select Bits
NCO Control <6:5>
SYNC Pin Used for Hop
Synchronization
00
SYNC0
01
SYNC1
10
SYNC2
11
SYNC3
<4>: This bit is open.
<3>: NCO Bypass Bit. When this bit is set, the NCO is bypassed
and shuts down for power savings. This bit can be used for
power savings, when NCO frequency of dc or 0 Hz is required.
When this bit is cleared, the NCO operates as programmed.
<2>: Clear NCO Accumulator Bit. When this bit is set, the clear
NCO accumulator bit synchronously clears the phase
accumulator on all frequency hops in this channel. When this
bit is cleared, the accumulator is not cleared and phase
continuous hops are implemented.
<1>: Phase Dither Enable Bit. When this bit is set, phase
dithering in the NCO is enabled. When this bit is cleared, phase
dithering is disabled.
<0>: Amplitude Dither Enable Bit. When this bit is set,
amplitude dithering in the NCO is enabled. When this bit is
cleared, amplitude dithering is disabled.
Channel Start Hold-Off Counter <15:0>
When a start synchronization (software or hardware) occurs on
the channel, the value in this register is loaded into a down-
counter. When the counter has finished counting down to 0, the
channel operation is started.
NCO Frequency Hop Hold-Off Counter <15:0>
When a hop sync occurs, a counter is loaded with the NCO
frequency hold-off register value. The 16-bit counter starts
counting down. When it reaches 0, the new frequency value in
the shadow register is written to the NCO frequency register.
(See the NCO Frequency Hold-Off Register section.)
NCO Frequency <31:0>
The value in this register is used to program the NCO tuning
frequency. The value to be programmed is given by the
following equation:
32
2
_
×
=
CLK
FREQUENCY
NCO
Register
Frequency
NCO
where:
NCO_FREQUENCY
is the desired NCO tuning frequency.
CLK
is the ADC clock rate.
The value given by the equation should be loaded into the
register in binary format.
NCO Phase Offset <15:0>
The value in the register is loaded into the phase accumulator of
the NCO block every time a start sync or hop sync is received
by the channel. This allows individual channels to be started
with a known nonzero phase. The NCO phase offset is not
loaded on a hop sync, if Bit <2> of the NCO control register
(clear phase accumulator on hop) is cleared. This NCO offset
register value is interpreted as a 16-bit unsigned integer. A
0x0000 in this register corresponds to a 0 radian offset, and a
0xFFFF corresponds to an offset of 2π (1 1/(216)) radians.
CIC Bypass <0>
When this bit is set, the entire CIC filter is bypassed. The output
of CIC filter is driven straight from the input without any
change. When this bit is cleared, the CIC filter operates in
normal mode as programmed. Writing Logic 1 to this bit
disables both the CIC decimation and CIC scaling operations.
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| AD6654BBCZ | 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654CBC | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
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| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
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