参数资料
| 型号： | AD6654BBC |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/88页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 92.16M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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AD6654
Rev. 0 | Page 51 of 88
Therefore, in the previous example, if the desired signal level is
13.8 dB, the request level R is programmed to be 16.54 dB,
compensating for the offset.
This request signal level is programmed in the 8-bit AGC
desired level register. This register has a floating-point
representation, where the 2 MSBs are exponent bits and the
6 LSBs are mantissa bits. The exponent is in steps of 6.02 dB,
and the mantissa is in steps of 0.094 dB. For example, a value
10’100101 represents 2 × 6.02 + 37 × 0.094 = 15.518 dB.
The AGC provides a programmable second-order loop filter.
The programmable parameters Gain 1 (K1), Gain 2 (K2), Error
Threshold E, and Pole P completely define the loop filter
characteristics. The error term after subtracting the request
signal level is processed by the loop filter, G(z). The open loop
poles of the second-order loop filter are 1 and P, respectively.
The loop filter parameters, Pole P and Gain K, allow the
adjustment of the filter time constant that determines the
window for calculating the peak-to-average ratio.
Depending on the value of the error term that is obtained after
subtracting the request signal level from the actual signal level,
either Gain Value K1 or Gain Value K2 is used. If the error is less
than the programmable threshold E, K1 or K2 is used. This
allows a fast loop when the error term is high (large
convergence steps required), and a slower loop function when
the error term is smaller (almost converged).
The open-loop gain used in the second-order loop G(z) is given
by one of the following equations:
K = K1, if Error < Error Threshold
K = K2, if Error > Error Threshold
The open-loop transfer function for the filter, including the gain
parameter, is
()
2
1
)
(
+
=
Pz
z
P
Kz
z
G
If the AGC is properly configured in terms of offset in the
request level, then there are no gains in the AGC loop except for
K, the filter gain. Under these circumstances, a closed-loop
expression for the AGC loop is given by
()
2
1
)
(
1
)
(
)
(
+
+
=
+
=
Pz
z
P
K
Kz
z
G
z
G
z
GCLOSED
Program K1 and K2 (the gain parameters) and Pole P through
AGC loop Gain 1 and Gain 2, and AGC pole location registers
from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For
example, 1000 1001 represent (137/256 = 0.535156). The error
threshold value is programmable between 0 dB and 96.3 dB in
steps of 0.024 dB. This value is programmed in the 12-bit AGC
error threshold register, using floating-point representation. It
consists of four exponent bits and eight mantissa bits. Exponent bits
are in steps of 6.02 dB and mantissa bits are in steps of 0.024 dB.
For example, 0111’10001001 represents 7 × 6.02 + 137 × 0.024 =
45.428 dB.
The user defines the open-loop Pole P and Gain K, which also
directly impact the placement of the closed-loop poles and filter
characteristics. These closed-loop poles, P1 and P2, are the roots
of the denominator of the previous closed-loop transfer
function and are given by
() (
)
2
4
1
,
2
P
K
P
K
P
2
1
+
±
+
=
Typically, the AGC loop performance is defined in terms of its
time constant or settling time. In this case, the closed-loop poles
should be set to meet the time constants required by the AGC
loop.
The relationship between the time constant and the closed-loop
poles that can be used for this purpose is
×
=
2
1,
CIC
1,2
Rate
Sample
M
P
τ
exp
where τ1, 2 are the time constants corresponding to Pole P1 and
Pole P 2
.
The time constants can also be derived from settling times as
given by
3
%
5
4
%
2
time
settling
or
time
settling
=
τ
MCIC (CIC decimation is from 1 to 4,096), and either the settling
time or time constant are chosen by the user. The sample rate is
the sample rate of the stream coming into the AGC. If channels
were interleaved in the output data router, then the combined
sample rate into the AGC should be considered. This rate
should be used in the calculation of poles in the previous
equation, where the sample rate is mentioned.
The loop filter output corresponds to the signal gain that is
updated by the AGC. Because all computation in the loop filter
is done in logarithmic domain (to the Base 2) of the samples,
the signal gain is generated using the exponent (power of 2) of
the loop filter output.
The gain multiplier gives the product of the signal gain with
both the I and Q data entering the AGC section. This signal
gain is applied as a coarse 4-bit scaling and then as a fine scale
8-bit multiplier. Therefore, the applied signal gain is from 0 to
96.3 dB in steps of 0.024 dB. The initial signal gain is program-
mable using the AGC signal gain register. This register is again a
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6654BBCZ | 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654CBC | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
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