- 您现在的位置：买卖IC网 > PDF目录16836 > AD9549A/PCBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9549A PDF资料下载
参数资料
| 型号： | AD9549A/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/76页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 设计资源： | AD9549 Schematics AD9549 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要属性： | 8 kHz ~ 750 MHz 输入 |
| 次要属性： | 差分输出 |
| 已供物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
AD9549
Rev. D | Page 25 of 76
The phase lock detect signal is generated once the control logic
observes that the output of the comparator has been in the true
Filter section for a description of the P-divider). When the phase
lock detect signal is asserted, it remains asserted until cleared
by an unlock event or by a device reset.
The duration of the lock detection process is programmable via
the phase lock watchdog timer bits. The interval is controlled by a
5-bit number, X (0 ≤ X ≤ 20).The absolute duration of the
phase lock detect interval is
S
X
LOCK
f
P
t
2
=
Hysteresis in the phase lock detection process is controlled by
specifying the minimum duration that qualifies as an unlock
event. An unlock event is declared when the control logic
observes that the output of the comparator has been in the false
state for 2Y + 1 periods of the P-divider clock (provided that the
phase lock detect signal has been asserted). Detection of an
unlock event clears the phase lock detect signal, and the phase
lock detection process is automatically restarted.
The time required to declare an unlock event is programmable
via the phase unlock watchdog timer bits. The interval is
controlled by a 3-bit number, Y (0 ≤ Y ≤ 7). The absolute
duration of the unlock detection interval is
S
Y
UNLOCK
f
P
t
1
2
+
=
Figure 31 shows the basic timing relationship between the
reference signal at the input to the phase detector, the phase
error magnitude, the output of the comparator, and the output
of the phase lock detector. The example shown here assumes
that X = 3 and Y = 1.
Note that the phase and frequency lock detectors may erroneously
indicate phase/frequency lock while in holdover. Therefore, the
user should use the phase and frequency lock signals in conjunc-
tion with either the reference input valid or the holdover active
signals to indicate phase/frequency lock.
Frequency Lock Detection
Frequency lock detection is similar to phase lock detection, with
the exception that the difference between successive phase
samples is the source of information. A running difference of
the phase samples serves as a digital approximation to the time-
derivative of the phase samples, which is analogous to frequency.
The formula for the frequency lock detect threshold value
(FLDT) is
×
=
2
7
10
_
10
2
round
R
f
R
Gain
FPFD
f
FLDT
where fR is the frequency of the active reference, R is the value of
the reference prescaler, and Δf is the maximum frequency
deviation of fR that is considered to indicate a frequency-locked
condition (Δf ≥ 0).
06744-
031
ABSOLUTE
VALUE
DIFFERENCER
DIGITAL
COMPARATOR
CONTROL LOGIC
UNLOCK
TIMER
LOCK
TIMER
FREQUENCY LOCK DETECT
THRESHOLD
Y
X
CLOSE
LOOP
FREQUENCY
LOCK
DETECT
RESET
P-DIVIDER
CLOCK
PHASE
DETECTOR
SAMPLES
I/O
REGISTERS
3
5
Figure 30. Frequency Lock Detection
06744-
030
fR/R
fS/P
0
THRESHOLD
COMPARATOR
PHASE ERROR
MAGNITUDE
SAMPLES
LOCK
TIMER
(X = 3)
UNLOCK
TIMER
(Y = 1)
8
4
LOCKED
THRESHOLD
Figure 31. Lock/Unlock Detection Timing
相关PDF资料 |
PDF描述 |
|---|---|
| ESC05DRTS-S734 | CONN EDGECARD 10POS DIP .100 SLD |
| MAX6250BEPA+ | IC VREF SERIES BURIED ZNR 8-PDIP |
| MAX6133A30+T | IC VREF SERIES PREC 3V 8-UMAX |
| MAX6133A41+T | IC VREF SERIES PREC 4.096V 8UMAX |
| MAX6133A50+T | IC VREF SERIES PREC 5V 8-UMAX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
| AD9549XCPZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9550 | 制造商:AD 制造商全称:Analog Devices 功能描述:Integer-N Clock Translator for Wireline Communications |
发布紧急采购，3分钟左右您将得到回复。