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参数资料
| 型号： | AD9549A/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/76页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 设计资源： | AD9549 Schematics AD9549 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要属性： | 8 kHz ~ 750 MHz 输入 |
| 次要属性： | 差分输出 |
| 已供物品： | 板 |
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AD9549
Rev. D | Page 31 of 76
Reference Validation Timers
Each of the two reference inputs has a dedicated validation
timer. The status of these timers is used by the holdover state
machine as part of the decision making process for reverting
to a previously faulty reference. For example, suppose that a
reference fails (that is, an LOR or OOL condition is in effect)
and that the device is programmed to revert automatically to
a valid reference when it recovers. When a reference returns to
normal operation, the LOR and OOL conditions are no longer
true. However, the state machine is not immediately notified of
the clearing of the LOR and OOL conditions. Instead, when
both the LOR and OOL conditions are cleared, the validation
timer for that particular reference is started. Expiration of the
validation timer is an indication to the state machine that the
reference is then available for selection. However, even though
the reference is then flagged as valid, actual transition to the
recovered reference depends on the programmed settings of the
various holdover control bits.
The validation timers are controlled via the I/O register map.
The user should be careful to make sure the validation timer is
at least two periods of the reference clock. Although there are
two independent validation timers, the programmed informa-
tion is shared by both. The desired time interval is controlled via
a 5-bit word (T) such that 0 ≤ T ≤ 31 (default is T = 0). The
duration of the validation timers is given by
(
)1
2 1
=
+
T
0
RECOVER
T
where T0 is the sample rate of the digital loop filter, whose
period is
S
P
0
f
T
IO
2
=
See the Digital Loop Filter section for more information.
Holdover Operation
When the holdover condition is asserted, the DDS output
frequency is no longer controlled by the phase lock feedback
loop. Instead, a static frequency tuning word (FTW) is applied
to the DDS to hold it at a specified frequency. The source of the
static FTW depends on the status of the appropriate control
register bits. During normal operation, the holdover averager and
sampler monitors and accumulates up to 65,000 FTW values as
they are generated, and, upon entering holdover, the holdover
state machine can use the averaged tuning word or the last valid
tuning word.
Exiting holdover mode is similar to the manner in which it is
entered. If manual holdover control is used, when the holdover
pin is deasserted, the phase detector starts comparing the
holdover signal with the reference input signal and starts to
adjust the phase/frequency using the holdover signal as its
starting point.
The behavior of the holdover state machine when it is automati-
cally exiting holdover mode is very similar. The primary
difference is that the reference monitor is continuously
monitoring both reference inputs and, as soon as one becomes
valid, the AD9549 automatically switches to that input.
The output frequency in holdover mode depends on the
frequency of the SYSCLK input source and the value of the
FTW applied to the DDS. Therefore, the stability of the output
signal is completely dependent on the stability of the SYSCLK
source (and the SYSCLK PLL multiplier, if enabled).
Note that it is very important to power down an unused
reference input to avoid chattering on that input. In addition,
the reference validation timer must be set to at least one full
cycle of the signal coming out of the reference divider.
Holdover Sampler and Averager (HSA)
If activated via the I/O register map, the HSA continuously
monitors the data generated by the digital loop filter in the
background. It should be noted that the loop filter data is a time
sequence of frequency adjustments (Δf) to the DDS. The output
of the HSA is routed to a read-only register in the I/O register
map and to the holdover control logic.
The first of these destinations (the read-only register) serves as
a trace buffer that can be read by the user and the data processed
externally. The second destination (the holdover control logic)
uses the output of the HSA to peg the DDS at a specific frequency
upon entry into the holdover state. Hence, the DDS assumes a
frequency specified by the last value generated by the HSA just
prior to entering the holdover state.
The state of the output mux is established by programming the
I/O register map. The default state is such that the Δf values
pass through the HSA unaltered. In this mode, the output sample
rate is fS/P, the same as the sample rate of the digital loop filter.
Note that P is the divide ratio of the P-divider (see the Digital
Alternatively, the mux can be set to select the averaging path.
In this mode, a block average is performed on a sequence of
samples. The length of the sequence is determined by program-
ming the value of Y (a 4-bit number stored in the I/O register
map) and has a value of 2Y+ 1. In averaging mode, the output
sample rate is given by fS/(P × 2Y +1).
When the number of Δf samples that are specified by Y has
been collected, the averaged result is delivered to a two-stage
pipeline. The last stage of the pipeline contains the value that
is delivered to the holdover control logic when a transition into
the holdover state occurs. The pipeline is a guarantee that the
averaged Δf value delivered to the holdover control logic has
not been interrupted by the transition into the holdover state.
The pipeline provides an inherent delay of Δt = P × 2Y+ 1/fS.
Hence, the DDS hold frequency is the average as it appeared Δt
to 2Δt seconds prior to entering the holdover state. Note that
the user has some control over the duration of Δt because it is
dependent on the programmed value of Y.
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