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| 型号： | AD9549A/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/76页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 设计资源： | AD9549 Schematics AD9549 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要属性： | 8 kHz ~ 750 MHz 输入 |
| 次要属性： | 差分输出 |
| 已供物品： | 板 |
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AD9549
Rev. D | Page 13 of 76
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, AVDD, AVDD3, and DVDD are at nominal supply voltage; fS = 1 GHz, DAC RSET = 10 kΩ.
06744-
003
10
100
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10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
RMS JITTER (12kHz TO 20MHz): 0.18ps
RMS JITTER (50kHz TO 80MHz): 0.24ps
Figure 3. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Bypassed), fREF = 19.44 MHz,
fOUT = 311.04 MHz, DPLL Loop BW = 1 kHz
06744-
004
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
RMS JITTER (12kHz TO 20MHz): 0.36ps
RMS JITTER (50kHz TO 80MHz): 0.42ps
Figure 4. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Bypassed), fREF = 19.44 MHz, fOUT = 622.08 MHz,
DPLL Loop BW = 1 kHz, HSTL Output Doubler Enabled
06744-
005
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
RMS JITTER (12kHz TO 20MHz): 1.01ps
RMS JITTER (50kHz TO 80MHz): 1.04ps
Figure 5. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled Driven by R&S SMA100 Signal Generator at 50 MHz),
fREF = 19.44 MHz, fOUT = 311.04 MHz, DPLL Loop BW = 1 kHz
06744-
006
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
RMS JITTER (12kHz TO 20MHz): 1.09ps
RMS JITTER (50kHz TO 80MHz): 1.14ps
Figure 6. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), fREF = 19.44 MHz, fOUT = 622.08 MHz, DPLL Loop BW = 1 kHz,
System Clock Doubler Enabled, HSTL Doubler Enabled
06744-
007
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
RMS JITTER (12kHz TO 20MHz): 1.0ps
RMS JITTER (50kHz TO 80MHz): 1.2ps
Figure 7. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 at 50 MHz), fREF = 19.44 MHz,
fOUT = 155.52 MHz, SYSCLK Doubler Enabled, DPLL Loop BW =1 kHz
06744-
008
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–70
–80
–90
–100
–110
–120
–130
–140
–150
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
RMS JITTER (12kHz TO 20MHz): 1.07ps
RMS JITTER (50kHz TO 80MHz): 1.16ps
Figure 8. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz
(SYSCLK PLL Enabled and Driven by R&S SMA100 Signal Generator at
50 MHz), fREF = 8 kHz, fOUT = 155.52 MHz, DPLL Loop BW = 10 Hz
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