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| 型号： | AD9549A/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/76页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 设计资源： | AD9549 Schematics AD9549 Gerber Files |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要属性： | 8 kHz ~ 750 MHz 输入 |
| 次要属性： | 差分输出 |
| 已供物品： | 板 |
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AD9549
Rev. D | Page 26 of 76
For example, if fR = 3 MHz, R = 5, FPFD_Gain = 200, and a fre-
quency lock threshold of 1% is specified, the frequency lock
detect threshold value is
(
)
667
,
170
10
3
5
200
10
2
10
3
%
1
round
2
6
7
10
6
=
×
=
FLDT
Hence, 170,667 (0x00029AAB) is the value that should be stored
in the frequency lock detect threshold bits.
The duration of the frequency lock/unlock detection process is
controlled in exactly the same way as the phase lock/unlock
detection process in the previous section. However, different
control registers are used: namely, the frequency lock/unlock
watchdog timer bits.
REFERENCE MONITORS
Loss of Reference
The AD9549 can set an alert when one or both of the reference
signals are not present. Each of the two reference inputs (REFA,
REFB) has a dedicated LOR (loss of reference) circuit enabled
via the I/O register map. Detection of an LOR condition sets the
appropriate LOR bit in both a status register and an IRQ status
register in the I/O register map. The LOR state is also internally
available to the multipurpose status pins (S1 to S4) of the AD9549.
By setting the appropriate bit in the I/O register map, the user
can assign a status pin to each of the LOR flags. This provides
a means to control external hardware based on the state of the
LOR flags directly.
The LOR circuits are internal watchdog timers that have a
programmable period. The period of the timer is set via the
I/O register map so that its period is longer than that of the
monitored reference signal. The rising edge of the reference
signal continuously resets the watchdog timer. If the timer
reaches a full count, this indicates that the reference was either
lost or its period was longer than the timer period. LOR does not
differentiate between these.
The period for each of the LOR timers is controlled by a 16-bit
word in the I/O register map. The period of the timer clock (tCLK)
is 2/fS. Therefore, the period of the watchdog timer (tWD) is
tWD = (2/fS)N
where N is the value of the 16-bit word stored in the I/O register
map for the appropriate LOR circuit.
Choose the value of N so that the watchdog period is greater
than the input reference period, expressed mathematically as
>
R
S
f
floor
N
2
where fR is the frequency of the input reference.
The value of N results in establishing two frequencies: one for
which the LOR signal is never triggered (fPRESENT), and one for
which the LOR signal is always active (fLOST). Using these fre-
quencies, the LOR signal intermittently toggles between states.
The values of the two frequency bounds are
)
1
(
2
=
N
f
S
PRESENT
N
f
S
LOST
2
=
Note that when N is chosen to be
1
2
floor
+
R
S
f
,
the LOR circuit is capable of indicating an LOR condition in
little more than a single input reference period. For example,
if fS = 1 GHz and fR = 2.048 MHz, then the smallest usable N
value is
245
1
)
10
048
.
2
(
2
10
floor
6
9
=
+
×
=
MIN
N
This yields the following values for fPRESENT and fLOST:
fPRESENT = 2,049,180
fLOST = 2,040,816
Note that N should be chosen sufficiently large to account for
any acceptable deviation in the period of the input reference
signal.
Notice that the value of N is inversely proportional to the
reference frequency, meaning that as the reference frequency
goes up, the precision for adjusting the threshold goes down.
Proper operation of the LOR circuit requires that N be no less
than 3. Therefore, the highest reference frequency for which the
LOR circuit functions properly is given by
6
S
LOR[MAX]
f
=
Reference Frequency Monitor
The AD9549 can set an alert whenever one or both of the
reference inputs drift in frequency beyond user-specified limits.
Each of the two references has a dedicated out of limits (OOL)
circuit enabled/disabled via the I/O register map. Detection of
an OOL condition sets the appropriate OOL bit in both a status
register and an IRQ status register in the I/O register map. The
user can also assign a status pin (S1 to S4) to each of the OOL
flags by setting the appropriate bit in the I/O register map. This
provides a means to control external hardware based on the
state of the OOL flags directly.
Each reference monitor contains three main building blocks: a
programmable reference divider, a 32-bit counter, and a 32-bit
digital comparator.
DIGITAL
COMPARATOR
32-BIT
COUNTER
16-BIT
OOL
DIVIDER
06744-
032
GATE
CLK
fS
fR
LOWER
LIMIT
UPPER
LIMIT
OOL
÷4
Figure 32. Reference Monitor
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