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参数资料
| 型号： | ADUC7021BCPZ62-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/92页 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 标准包装： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 13 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b，D/A 2x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 52 of 92
Example source code:
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
// Set Core into Nap mode
POWKEY2 = 0xF4;
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is only serviced when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1. The external clock can be up to 44 MHz, providing
the tolerance is 1%.
Example source code:
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
3)) //ensures timer value loaded
IRQEN = 0x10;
//enable T2 interrupt
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
//
Set Core into Nap mode
POWKEY2 = 0xF4;
Power Control System
A choice of operating modes is available on the ADuC7019/20/
21/22/24/25/26/27/28. Table 31 describes what part is powered
on in the different modes and indicates the power-up time.
Table 32 gives some typical values of the total current consump-
tion (analog + digital supply currents) in the different modes,
depending on the clock divider bits. The ADC is turned off. Note
that these values also include current consumption of the
regulator and other parts on the test board where these values
are measured.
Table 31. Operating Modes
Mode
Core
Peripherals
PLL
XTAL/T2/T3
IRQ0 to IRQ3
Start-Up/Power-On Time
Active
X
130 ms at CD = 0
Pause
X
24 ns at CD = 0; 3 μs at CD = 7
Nap
X
24 ns at CD = 0; 3 μs at CD = 7
Sleep
X
1.58 ms
Stop
X
1.7 ms
Table 32. Typical Current Consumption at 25°C in mA.
PC[2:0]
Mode
CD = 0
CD = 1
CD = 2
CD = 3
CD = 4
CD = 5
CD = 6
CD = 7
000
Active
33.1
21.2
13.8
10
8.1
7.2
6.7
6.45
001
Pause
22.7
13.3
8.5
6.1
4.9
4.3
4
3.85
010
Nap
3.8
011
Sleep
0.4
100
Stop
0.4
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