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| 型号： | ADUC7021BCPZ62-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 60/92页 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 标准包装： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 13 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b，D/A 2x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 63 of 92
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the value
in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
DL
Rate
Baud
CD
×
=
2
16
2
MHz
78
.
41
Table 48 gives some common baud rate values.
Table 48. Baud Rate Using the Normal Baud Rate Generator
Baud Rate
CD
DL
Actual Baud Rate
% Error
9,600
0
0x88
9,600
0
19,200
0
0x44
19,200
0
115,200
0
0x0B
118,691
3
9,600
3
0x11
9600
0
19,200
3
0x08
20,400
6.25
115,200
3
0x01
163,200
41.67
The Fractional Divider
The fractional divider, combined with the normal baud rate
generator, produces a wider range of more accurate baud rates.
04
95
5-
03
2
/16DL
UART
FBEN
CORE
CLOCK
/2
/(M+N/2048)
Figure 62. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as follows:
+
×
=
2048
2
16
2
MHz
78
.
41
N
M
DL
Rate
Baud
CD
2
16
2
MHz
78
.
41
2048
×
=
+
DL
Rate
Baud
N
M
CD
For example, generation of 19,200 baud with CD bits = 3
(Table 48 gives DL = 0x08), is
2
8
16
2
19200
MHz
78
.
41
2048
3
×
=
+ N
M
06
.
1
2048
=
+ N
M
where:
M = 1
N = 0.06 × 2048 = 128
×
=
2048
128
2
8
16
2
MHz
78
.
41
3
Rate
Baud
where:
Baud Rate = 19,200 bps
Error = 0%, compared to 6.25% with the normal baud rate
generator.
UART Register Definitions
The UART interface consists of 12 registers: COMTX, COMRX,
COMDIV0, COMIEN0, COMDIV1, COMIID0, COMCON0,
COMCON1, COMSTA0, COMSTA1, COMSCR, and
COMDIV2.
COMTX Register
Name
Address
Default Value
Access
COMTX
0xFFFF0700
0x00
R/W
COMTX is an 8-bit transmit register.
COMRX Register
Name
Address
Default Value
Access
COMRX
0xFFFF0700
0x00
R
COMRX is an 8-bit receive register.
COMDIV0 Register
Name
Address
Default Value
Access
COMDIV0
0xFFFF0700
0x00
R/W
COMDIV0 is a low byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
COMIEN0 Register
Name
Address
Default Value
Access
COMIEN0
0xFFFF0704
0x00
R/W
COMIEN0 is the interrupt enable register.
Table 49. COMIEN0 MMR Bit Descriptions
Bit
Name
Description
7:4
–
Reserved.
3
EDSSI
Modem Status Interrupt Enable Bit. Set by
user to enable generation of an interrupt if
any of COMSTA1[3:1] are set. Cleared by user.
2
ELSI
Rx Status Interrupt Enable Bit. Set by user to
enable generation of an interrupt if any of
COMSTA0[3:0] are set. Cleared by user.
1
ETBEI
Enable Transmit Buffer Empty Interrupt. Set
by user to enable interrupt when buffer is
empty during a transmission. Cleared by user.
0
ERBFI
Enable Receive Buffer Full Interrupt. Set by
user to enable interrupt when buffer is full
during a reception. Cleared by user.
COMDIV1 Register
Name
Address
Default Value
Access
COMDIV1
0xFFFF0704
0x00
R/W
COMDIV1 is a divisor latch (high byte) register.
COMIID0 Register
Name
Address
Default Value
Access
COMIID0
0xFFFF0708
0x01
R
COMIID0 is the interrupt identification register.
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