- 您现在的位置：买卖IC网 > PDF目录1900 > ADUC7021BCPZ62-RL7 (Analog Devices Inc)IC MCU 12BIT 1MSPS UART 40-LFCSP PDF资料下载
参数资料
| 型号： | ADUC7021BCPZ62-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 64/92页 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 标准包装： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 13 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b，D/A 2x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页当前第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 67 of 92
Table 59. SPISTA MMR Bit Descriptions
Bit
Description
7:6
Reserved.
5
SPIRX Data Register Overflow Status Bit. Set if SPIRX is
overflowing. Cleared by reading SPIRX register.
4
SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
3
SPIRX Data Register Full Status Bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
2
SPITX Data Register Underflow Status Bit. Set auto-
matically if SPITX is underflowing. Cleared by writing in
the SPITX register.
1
SPITX Data Register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
0
SPITX Data Register Empty Status Bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
SPIRX Register
Name
Address
Default Value
Access
SPIRX
0xFFFF0A04
0x00
R
SPIRX is an 8-bit read-only receive register.
SPITX Register
Name
Address
Default Value
Access
SPITX
0xFFFF0A08
0x00
W
SPITX is an 8-bit write-only transmit register.
SPIDIV Register
Name
Address
Default Value
Access
SPIDIV
0xFFFF0A0C
0x1B
R/W
SPIDIV is an 8-bit serial clock divider register.
SPICON Register
Name
Address
Default Value
Access
SPICON
0xFFFF0A10
0x0000
R/W
SPICON is a 16-bit control register.
Table 60. SPICON MMR Bit Descriptions
Bit
Description
Function
15:13
Reserved.
–
12
Continuous Transfer
Enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is
available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial
transfer until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a
single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a
stall period.
11
Loop Back Enable.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
10
Slave Output Enable.
Set by user to enable the slave output enable. Cleared by user to disable slave output enable.
9
Slave Select Input Enable.
Set by user in master mode to enable the output. Cleared by user to disable master output.
8
SPIRX Overflow
Overwrite Enable.
Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by
user, the new serial byte received is discarded.
7
SPITX Underflow Mode.
Set by user to transmit 0. Cleared by user to transmit the previous data.
6
Transfer and Interrupt
Mode.
Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full.
5
LSB First Transfer
Enable Bit.
Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
4
Reserved.
–
3
Serial Clock Polarity
Mode Bit.
Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
2
Serial Clock Phase
Mode Bit.
Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial
clock pulses at the end of each serial bit transfer.
1
Master Mode Enable Bit.
Set by user to enable master mode. Cleared by user to enable slave mode.
0
SPI Enable Bit.
Set by user to enable the SPI. Cleared by user to disable the SPI.
相关PDF资料 |
PDF描述 |
|---|---|
| ADUC7023BCPZ62I-R7 | IC MCU 12BIT 62KB FLASH 32LFCSP |
| ADUC7024BCPZ62 | IC MCU FLSH 62K ANLG I/O 64LFCSP |
| ADUC7032BSTZ-88 | IC MCU 96K FLASH DUAL 48LQFP |
| ADUC7032BSTZ-8V-RL | IC BATTERY SENSOR PREC 48-LQFP |
| ADUC7034BCPZ | IC MCU FLASH 32K ANLG IO 48LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADUC7022 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| ADUC7022ACP32 | 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC IC - Trays |
| ADUC7022ACPZ32 | 制造商:Analog Devices 功能描述:MCU 32BIT RISC 32KB FLASH 3.3V 40LFCSP EP - Trays |
| ADUC7022BCP32 | 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC IC - Trays |
| ADUC7022BCP62 | 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC IC - Trays |
发布紧急采购，3分钟左右您将得到回复。