参数资料
型号: ADUC7032BSTZ-8V-RL
厂商: Analog Devices Inc
文件页数: 113/128页
文件大小: 0K
描述: IC BATTERY SENSOR PREC 48-LQFP
标准包装: 1
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 20.48MHz
连通性: LIN,SPI,UART/USART
外围设备: POR,PSM,温度传感器,WDT
输入/输出数: 9
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 1.5K x 32
电压 - 电源 (Vcc/Vdd): 3.5 V ~ 18 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 标准包装
其它名称: ADUC7032BSTZ-8V-RLDKR
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 85 of 128
Timer3 Clear Register :
Name :
T3CLRI
Address :
0xFFFF036C
Default Value :
0x00
Access :
Write Only
Function :
This 16-bit, write-only MMR is written
(with any value) by user code to refresh(reload) Timer3 in
watchdog mode to prevent a watchdog timer reset event. This
register must be written with a specific value (generated by user
code, based on a polynomial equation) to refresh the watchdog
timer and prevent a watchdog reset.
Timer3 Control Register :
Name :
T3CON
Address :
0xFFFF0368
Default Value :
0x00
Access :
Read/Write Once Only
Function :
The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 47.
Table 47 : T3CON MMR Bit Definition
Bit
Description
16-9
These bits are reserved and should be written as 0 by user code
8
Count Up/Down Enable
Set by user code to configure Timer3 to count up
Cleared by user code to configure Timer3 to count down.
7
Timer3 Enable
Set by user code to enable Timer 3
Cleared by user code to disable Timer 3. .
6
Timer3 Operating Mode
Set by user code to configure Timer3 to operate in periodic mode
Cleared by user to configure Timer3 to operate in free-running mode.
5
Watchdog Timer Mode Enable
Set by user code to enable watchdog mode
Cleared by user code to disable watchdog mode.
4
This bit is reserved and should be written as 0 by user code
3-2
Timer3 Clock(32.768kHz) Pre-Scalar
00
Source clock / 1 ( Default )
01
Source clock / 16
10
Source clock / 256
11
Reserved
1
Watchdog Timer IRQ Enable
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0
Cleared by user code to disable the IRQ option.
0
PD_OFF
Set by the user code to stop Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
Cleared by the user code to enable Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
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