
Preliminary Technical Data
ADuC7032
Rev. PrD | Page 60 of 128
bit is set in the ADCSTA MMR generating an ADC interrupt.
The I-ADC Comparator Threshold bit is asserted as soon as the
ADC0THV=ADC0TCL.
Current Channel ADC Threshold Count Register:
Name :
ADC0THV
Address :
0xFFFF0558
Default Value :
0x00
Access :
Read Only
Function :
This 8-bit MMR is incremented every time
the absolute value of an I-ADC conversion result |I| >=
ADC0TH. This register is decremented or reset to 0 every time
the absolute value of an I-ADC conversion result |I| <
ADC0TH. The configuration of this function is enabled via the
Current Channel ADC Comparator bits in the ADCCFG MMR
Current Channel ADC Accumulator Register:
Name :
ADC0ACC
Address :
0xFFFF055C
Default Value :
0x00000000
Access :
Read Only
Function :
This 32-bit MMR holds the current
accumulator value. The I-ADC READY bit in the ADCSTA
MMR should be used to determine when it is safe to read this
MMR. The MMR value is reset to 0 by disabling the
accumulator in the ADCCFG MMR or reconfiguring the
Current Channel ADC.
Current Channel ADC Accumulator Threshold
Register:
Name :
ADC0ATH
Address :
0xFFFF0560
Default Value :
0x00000000
Access :
Read/Write
Function :
This 32-bit MMR sets the threshold against
which the accumulated value of the I-ADC results is compared.
In Unipolar mode ADC0TH [15:0] are compared and in 2’s
compliment mode ADC0TH[14:0] are compared.
Low Power Voltage Reference Scaling Factor
Name :
ADCREF
Address :
0xFFFF057C
Default Value :
Part Specific, factory programmed
Access :
Read
Function :
This allows user code to correct for the
initial error of the LPM reference. The default value of 0x8000
corresponds to no error when compared to the Normal Mode
Reference.
If the LPM Voltage Reference is 1% below1.200V,then the value
of ADCREF will be approximately 0x7EB9
If the LPM Voltage Reference is 1% above1.200V,then the value
of ADCREF will be approximately 0x8147
ADC POWER MODES OF OPERATION
The ADCs can be configured into various reduced or full
‘power’ modes of operation by configuring ADCMDE[4:3] as
appropriate. The ARM7 MCU can itself also be configured in
Low Power modes of operation (POWCON[5:3]). The core
power modes are independently controlled and are not related
to the ADC power modes described here. The ADC power
modes of operation are described in more detail below.
Every I-ADC result can also compared to a pre-set threshold
level (ADC0TH) as configured via ADCCFG[4:3]. An MCU
interrupt is generated if the absolute (sign-independent) value
of the ADC result is greater than the pre-programmed
comparator threshold level. An extended function of this
comparator function allows user code to configure a threshold
counter (ADC0THV) which monitors the number of I-ADC
results that have occurred above or below the pre-set threshold
level. Again an ADC interrupt is generated once the threshold
counter reaches a pre-set value (ADC0TCL).
Finally, a 32-bit accumulator(ADC0ACC) function can be
configured(ADCCFG[6:5]) allowing the I-ADC to add(or
subtract) multiple I-ADC sample results. User code can read
the accumulated value directly( via ADC0ACC) without any
further software processing.
ADC Startup Procedure
Prior to beginning converting, the following procedure should
be followed.
1.
Configure the Current ADC, ADC0, into Low-Power-
Mode
(ADC0CON = 0x8007; ADCMDE = 0x09)
2.
Delay for 200us.
3.
Switch the Current ADC, ADC0, into Idle-Mode
(ADCMDE = 0x03), keeping ADC0CON unchanged.
If the Voltage or Temperature channels are to be
used, they should be enabled here.
4.
Delay for 1ms
5.
Switch ADCMDE to desired mode,
e.g. ADC0CON = 0x1.