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参数资料
型号： DS2196LN+
厂商： Maxim Integrated Products
文件页数： 119/157页
文件大小： 0K
描述： IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 90
控制器类型： T1 调帧器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 85mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-LQFP（14x14）
包装： 托盘
DS2196
64 of 157
IMR2B: INTERRUPT MASK REGISTER 2 FRAMER B (Address = EF Hex)
(MSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
–
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
IMR2B.7
Receive Multiframe.
0 = interrupt masked
1 = interrupt enabled
TMF
IMR2B.6
Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
SEC
IMR2B.5
One Second Timer.
0 = interrupt masked
1 = interrupt enabled
RFDL
IMR2B.4
Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
TFDL
IMR2B.3
Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
RMTCH
IMR2B.2
Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
RAF
IMR2B.1
Receive FDL Abort.
0 = interrupt masked
1 = interrupt enabled
–IMR2B.0
Not Assigned. Should be set to 0 when written to.
8. ERROR COUNT REGISTERS
There is a set of three counters per framer that record bipolar violations, excessive zeros, errors in the
CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive
synchronization. Each of these three counters can be automatically updated on either one second
boundaries (CCR3.2=0) or every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2
(SR2.5) or manually (CCR6.6=1 and triggering with CCR6.5). When updated automatically, the user
can use the interrupt from the one-second timer to determine when to read these registers. The user has a
full second (or 42 ms) to read the counters before the data is lost. All three counters will saturate at their
respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register
has the potential to over-flow but the bit error would have to exceed 10E-2 before this would occur).
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