参数资料
型号: DS2196LN+
厂商: Maxim Integrated Products
文件页数: 66/157页
文件大小: 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 85mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
DS2196
16 of 157
Parallel Control Port Pins
Signal Name:
INT*
Signal Description:
Interrupt
Signal Type:
Output
Flags host controller during conditions and change of states as defined in the Status Registers. Active low, open
drain output.
Signal Name:
MUX
Signal Description:
Bus Operation
Signal Type:
Input
Set low to select non-multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
D0 to D7 / AD0 to AD7
Signal Description:
Data Bus or Address/Data Bus
Signal Type:
Input / Output
In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1),
serves as a 8–bit multiplexed address / data bus.
Signal Name:
A0 to A6
Signal Description:
Address Bus
Signal Type:
Input
In non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1),
these pins are not used and should be tied low.
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the
RD*(DS*), ALE (AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis
().
Signal Name:
RD* (DS*)
Signal Description:
Read Input (Data Strobe)
Signal Type:
Input
RD* is an active low signal. DS* polarity is determined by the MUX pin setting. Refer to section 21 for details.
Signal Name:
CS*
Signal Description:
Chip Select
Signal Type:
Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name:
ALE(AS) / A7
Signal Description:
A7 or Address Latch Enable (Address Strobe)
Signal Type:
Input
In non-multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX
= 1), serves to demultiplex the bus on a positive–going edge.
Signal Name:
WR*( R/W*)
Signal Description:
Write Input (Read/Write)
Signal Type:
Input
WR* is an active low signal.
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