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参数资料
型号： DS2196LN+
厂商： Maxim Integrated Products
文件页数： 155/157页
文件大小： 0K
描述： IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 90
控制器类型： T1 调帧器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 85mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-LQFP（14x14）
包装： 托盘
DS2196
97 of 157
ERCA: ERROR RATE CONTROL REGISTER FRAMER A (Address = 80 Hex)
ERCB: ERROR RATE CONTROL REGISTER FRAMER A (Address = 85 Hex)
(MSB)
(LSB)
WNOE
RNOE
TCBE
CE
ER3
ER2
ER1
ER0
SYMBOL
POSITION
NAME AND DESCRIPTION
WNOE
ERC.7
Write NOE Registers. If the Host wishes to update to the
NOE registers, this bit must be toggled from a 0 to a 1 after
the Host has already loaded the prescribed error count into the
NOE registers. The toggling of this bit causes the error count
loaded into the NOE registers to be loaded into the error
insertion circuitry on the next clock cycle.
Subsequent
updates require that the WNOE bit be set to 0 and then 1 once
again.
RNOE
ERC.6
Read RNOEL Registers. If the Host wishes to obtain the
latest count of the number of errors left to be inserted by the
error insertion function, then this bit must be toggled from a 0
to a 1. Subsequent reads require that the RNOE bit be set to 0
and then 1 once again. The Host must wait at least 972 ns
(1.5 clock periods) after toggling this bit to read the NOEL
registers. The Host may read the NOEL registers at any time
but they will contain either the count of errors left to be
inserted (after toggling the RNOE bit) or the count of the
number of errors that the Host has loaded (after writing to the
NOE registers).
TCBE
ERC.5
TCHBLK Enable.
This bit determines whether the
TCHBLK signal should be used to “block” certain channels
from being corrupted. When TCBE is set high, then the error
insertion logic will not corrupt DS0 channels in which the
TCHBLK signal has be programmed high.
0 = all the error insertion logic to corrupt all DS0 channels
1 = allow the error insertion logic to only corrupt the DS0
channels determined by
the TCHBLK signal
CE
ERC.4
Constant Errors. When this bit is set high (and the ER0 to
ER3 bits are not set to 0000), the error insertion logic will
ignore the Number Of Error registers (NOE1A, NOE2A,
NOE1B, and NOE2B) and generate errors constantly at the
selected insertion rate.
When CE is set to 0, the NOE
registers determine how many errors are to be inserted.
ER3
ERC.3
Error Rate Bit 3. Refer to Table 16-1 for details.
ER2
ERC.2
Error Rate Bit 2. Refer to Table 16-1 for details.
ER1
ERC.1
Error Rate Bit 1. Refer to Table 16-1 for details.
ER0
ERC.0
Error Rate Bit 0. Refer to Table 16-1 for details.
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