DS2196LN+ (Maxim) PDF资料下载 Datasheet(4/157 页)

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型号：	DS2196LN+
厂商：	Maxim Integrated Products
文件页数：	4/157页
文件大小：	0K
描述：	IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	90
控制器类型：	T1 调帧器
接口：	并行/串行
电源电压：	3.135 V ~ 3.465 V
电流 - 电源：	85mA
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	100-LQFP
供应商设备封装：	100-LQFP（14x14）
包装：	托盘

DS2196

101 of 157

18.

FDL/Fs EXTRACTION AND INSERTION

Each Framer/Formatter has the ability to extract/insert data from/ into the Facility Data Link (FDL) in the

ESF framing mode and from/into Fs–bit position in the D4 framing mode. Since SLC–96 utilizes the

Fs-bit position, this capability can also be used in SLC–96 applications. The DS2196 contains a complete

HDLC and BOC controller for the FDL and this operation is covered in Section 18.1. To allow for

backward compatibility between the DS2196 and earlier devices, the DS2196 maintains some legacy

functionality for the FDL and this is covered in Section 18.2. Section 18.3 covers D4 and SLC–96

operation. Please contact the factory for a copy of C language source code for implementing the FDL on

the DS2196.

18.1HDLC AND BOC CONTROLLER FOR THE FDL

18.1.1 General Overview

The DS2196 contains a complete HDLC controller with 64–byte buffers in both the transmit and receive

directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller

performs all the necessary overhead for generating and receiving Performance Report Messages (NPRMs

and SPRMs) as described in ANSI T1.403-1998 and the messages as described in AT&T TR54016. The

HDLC controller automatically generates and detects flags, generates and checks the CRC check sum,

generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the

HDLC data stream. The 64–byte buffers in the HDLC controller are large enough to allow a full NPRM

or SPRM to be received or transmitted without host intervention. The BOC controller will automatically

detect incoming BOC sequences and alert the host. When the BOC ceases, the DS2196 will also alert the

host.

The user can set the device up to send any of the possible 6–bit BOC codes.

There are thirteen registers that the host will use to operate and control the operation of the HDLC and

BOC controllers. A brief description of the registers is shown in Table 18–1.

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