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参数资料
型号： DS2196LN+
厂商： Maxim Integrated Products
文件页数： 138/157页
文件大小： 0K
描述： IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 90
控制器类型： T1 调帧器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 85mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-LQFP（14x14）
包装： 托盘
DS2196
81 of 157
RDNCD2A: RECEIVE DOWN CODE DEFINITION REGISTER 2 FRAMER A
(Address = 18 Hex)
RDNCD2B: RECEIVE DOWN CODE DEFINITION REGISTER 2 FRAMER B
(Address = B8 Hex)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
RDNCD2.7
Receive Down Code Definition Bit 7. A Don’t Care if a 1 to
7 bit length is selected.
C6
RDNCD2.6
Receive Down Code Definition Bit 6. A Don’t Care if a 1 to
7 bit length is selected.
C5
RDNCD2.5
Receive Down Code Definition Bit 5. A Don’t Care if a 1 to
7 bit length is selected.
C4
RDNCD2.4
Receive Down Code Definition Bit 4. A Don’t Care if a 1 to
7 bit length is selected.
C3
RDNCD2.3
Receive Down Code Definition Bit 3. A Don’t Care if a 1 to
7 bit length is selected.
C2
RDNCD2.2
Receive Down Code Definition Bit 2. A Don’t Care if a 1 to
7 bit length is selected.
C1
RDNCD2.1
Receive Down Code Definition Bit 1. A Don’t Care if a 1 to
7 bit length is selected.
C0
RDNCD2.0
Receive Down Code Definition Bit 0. A Don’t Care if a 1 to
7 bit length is selected.
RSCCA: IN–BAND RECEIVE SPARE CONTROL REGISTER FRAMER A
(Address = 1D Hex)
RSCCB: IN–BAND RECEIVE SPARE CONTROL REGISTER FRAMER B
(Address = BD Hex)
(MSB)
(LSB)
–––––
RSC2
RSC1
RSC0
SYMBOL
POSITION
NAME AND DESCRIPTION
–
RSCC.7
Not Assigned. Should be set to 0 when written to.
–
RSCC.6
Not Assigned. Should be set to 0 when written to.
–
RSCC.5
Not Assigned. Should be set to 0 when written to.
–
RSCC.4
Not Assigned. Should be set to 0 when written to.
–
RSCC.3
Not Assigned. Should be set to 0 when written to.
RSC2
RSCC.2
Receive Spare Code Length Definition Bit 2. See Table 12–2
RSC1
RSCC.1
Receive Spare Code Length Definition Bit 1. See Table 12–2
RSC0
RSCC.0
Receive Spare Code Length Definition Bit 0. See Table 12–2
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