参数资料
型号: DS2196LN+
厂商: Maxim Integrated Products
文件页数: 143/157页
文件大小: 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 85mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
DS2196
86 of 157
15.
BERT FUNCTION
The BERT Block can generate and detect both pseudorandom and repeating bit patterns and it is used to
test and stress data communication links.
The BERT Block is capable of generating and detected the following patterns:
The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words which flip every 1 to 256 words
Daly pattern
The BERT receiver has a 32-bit Bit Counter and a 24-bit Error Counter. The BERT receiver will report
three events, a change in receive synchronizer status, a bit error being detected, and if either the Bit
Counter or the Error Counter overflows. Each of these events can be masked within the BERT function
via the BERT Control Register 1 (BC1). If the software detects that the BERT has reported an event has
occurred, then the software must read the BERT Information Register (BIR) to determine which event(s)
has occurred. To activate the BERT Block, the Host must configure the BERT mux via the BIC register
(see Figure 15-1).
The BERT INTERRUPT REQUEST (BIRQ) status bit located at ISR.6 will be set to a 1 if there is a
major change of state in the BERT receiver. A major change of state is defined as either a change in the
receive synchronization (i.e. the BERT has gone into or out of receive synchronization), a bit error has
been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The Host must
read the status bits of the BERT in the BERT Information Register (BIR) to determine the change of
state. The BIRQ bit will be cleared when read and will not be set again until the BERT has experienced
another change of state.
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