参数资料
型号: DS2196LN+
厂商: Maxim Integrated Products
文件页数: 25/157页
文件大小: 0K
描述: IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 85mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
DS2196
120 of 157
Table 19-2: TRANSFORMER SPECIFICATIONS
SPECIFICATION
RECOMMENDED VALUE
Turns Ratio
1:1(receive) and 1:2(transmit) 5%
Primary Inductance
600
mH minimum
Leakage Inductance
1.0
mH maximum
Intertwining Capacitance
40 pF maximum
Transmit Transformer DC Resistance
Primary (Device side)
Secondary
1.0
W maximum
2.0
W maximum
Receive Transformer DC Resistance
Primary (Device side)
Secondary
1.2
W maximum
1.2
W maximum
19.3JITTER ATTENUATOR
The DS2196 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the
JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 19–4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In
order for the jitter attenuator to operate properly, a 1.544 MHz clock (50 ppm) must be applied at the
MCLK pin. Onboard circuitry adjusts either the recovered clock from the clock/data recovery block or
the clock applied at the TCLKLI pin to create a smooth jitter free clock which is used to clock data out of
the jitter attenuator FIFO. It is acceptable to provide a gapped/ bursty clock at the TCLKLI pin if the
jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIpp (buffer
depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2196 will divide the internal nominal
24.704 MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing.
When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the
Receive Information Register (RIR3.5)
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