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参数资料
型号： DS2196LN+
厂商： Maxim Integrated Products
文件页数： 128/157页
文件大小： 0K
描述： IC FRAMER DUAL T1 LIU 100-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 90
控制器类型： T1 调帧器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 85mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-LQFP（14x14）
包装： 托盘
DS2196
72 of 157
RDS0MA: RECEIVE DS0 MONITOR REGISTER FRAMER A
(Address = 1F Hex)
RDS0MB: RECEIVE DS0 MONITOR REGISTER FRAMER B
(Address = BF Hex)
(MSB)
(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION
NAME AND DESCRIPTION
B1
RDS0M.7
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be received).
B2
RDS0M.6
Receive DS0 Channel Bit 2.
B3
RDS0M.5
Receive DS0 Channel Bit 3.
B4
RDS0M.4
Receive DS0 Channel Bit 4.
B5
RDS0M.3
Receive DS0 Channel Bit 5.
B6
RDS0M.2
Receive DS0 Channel Bit 6.
B7
RDS0M.1
Receive DS0 Channel Bit 7.
B8
RDS0M.0
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
11.
PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
The DS2196 can replace data on a channel–by–channel basis in both the transmit and receive directions.
The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive
direction is from the T1 line to the backplane and is covered in Section 11.2.
11.1TRANSMIT SIDE CODE GENERATION
The Transmit Idle Registers (TIR1/2/3) are used to determine which of the 24 T1 channels should be
overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows
the same 8–bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0
control bit must be set to 0.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Bit 7 stuffing will occur over the programmed
Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
Loopback (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RSYNC to
TSYNC.
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