收藏本站
参数资料
型号： DSPB56362AG120
厂商： Freescale Semiconductor
文件页数： 124/152页
文件大小： 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
标准包装： 60
系列： DSP56K/Symphony
类型： 音频处理器
接口： 主机接口，I²C，SAI，SPI
时钟速率： 120MHz
非易失内存： ROM（126 kB）
芯片上RAM： 42kB
电压 - 输入/输出： 3.30V
电压 - 核心： 3.30V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 144-LQFP
供应商设备封装： 144-LQFP（20x20）
包装： 托盘
Parallel Host Interface (HDI08) Timing
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-47
333
HCS hold time after data strobe deassertion9
—0.0
—
ns
334
Address (AD7–AD0) setup time before HAS deassertion
(HMUX=1)
—4.7
—
ns
335
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
—
3.3
—
ns
336
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before
data strobe assertion9
Read
Write
—
0
4.7
—
ns
337
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after
data strobe deassertion9
—3.3
—
ns
338
Delay from read data strobe deassertion to host request
assertion for “Last Data Register” read4, 5, 10
TC
10
—
ns
339
Delay from write data strobe deassertion to host request
assertion for “Last Data Register” write5, 8, 10
2
× T
C
20
—
ns
340
Delay from data strobe assertion to host request deassertion for
“Last Data Register” read or write (HROD = 0)5, 9, 10
——
19.1
ns
341
Delay from data strobe assertion to host request deassertion for
“Last Data Register” read or write (HROD = 1, open drain Host
Request)5, 9, 10, 11
—
300.0
ns
342
Delay from DMA HACK deassertion to HOREQ assertion
For “Last Data Register” read5
For “Last Data Register” write5
For other cases
2
× T
C + 19.1
1.5
× T
C + 19.1
39.1
34.1
0.0
—
ns
343
Delay from DMA HACK assertion to HOREQ deassertion
HROD = 05
—
—20.2
ns
344
Delay from DMA HACK assertion to HOREQ deassertion for
“Last Data Register” read or write
HROD = 1, open drain Host Request5, 11
—
300.0
ns
1 See Host Port Usage Considerations in the DSP56362 User Design Manual.
2 In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3 V
CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF
4 The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
5 The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1).
6 This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
7 This timing is applicable only if two consecutive reads from one of these registers are executed.
Table 3-20 Host Interface (HDI08) Timing1, 2 (continued)
No.
Characteristics3
Expression
100 MHz
Unit
Min
Max
相关PDF资料
PDF描述
DSPB56364AF100 IC DSP 24BIT AUD 100MHZ 100-LQFP
DSPB56366AG120 IC DSP 24BIT AUD 120MHZ 144-LQFP
DSPB56367AG150 IC DSP 24BIT 150MHZ 144-LQFP
DSPB56371AF180 IC DSP 24BIT 180MHZ 80-LQFP
DSPB56374AEC IC DSP 24BIT 150MHZ 52-LQFP
相关代理商/技术参数
参数描述
DSPB56362AG120 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
DSPB56362PV100 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk
DSPB56362PV120 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk
DSPB56364AF100 功能描述:数字信号处理器和控制器 - DSP, DSC DSP56364 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPB56364FU100 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*