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参数资料
型号： DSPB56362AG120
厂商： Freescale Semiconductor
文件页数： 24/152页
文件大小： 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
标准包装： 60
系列： DSP56K/Symphony
类型： 音频处理器
接口： 主机接口，I²C，SAI，SPI
时钟速率： 120MHz
非易失内存： ROM（126 kB）
芯片上RAM： 42kB
电压 - 输入/输出： 3.30V
电压 - 核心： 3.30V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 144-LQFP
供应商设备封装： 144-LQFP（20x20）
包装： 托盘
External Memory Expansion Port (Port A)
DSP56362 Technical Data, Rev. 4
2-6
Freescale Semiconductor
2.5.3
External Bus Control
Table 2-7 External Bus Control Signals
Signal Name
Type
State during Reset
Signal Description
AA0–AA3/RA
S0–RAS3
Output
Tri-Stated
Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When
defined as RAS, these signals can be used as RAS for DRAM interface.
These signals are can be tri-stated outputs with programmable polarity.
CAS
Output
Tri-Stated
Column Address Strobe—When the DSP is the bus master, CAS is an
active-low output used by DRAM to strobe the column address. Otherwise,
if the bus mastership enable (BME) bit in the DRAM control register is
cleared, the signal is tri-stated.
RD
Output
Tri-Stated
Read Enable—When the DSP is the bus master, RD is an active-low output
that is asserted to read external memory on the data bus (D0–D23).
Otherwise, RD is tri-stated.
WR
Output
Tri-Stated
Write Enable—When the DSP is the bus master, WR is an active-low
output that is asserted to write external memory on the data bus (D0–D23).
Otherwise, the signals are tri-stated.
TA
Input
Ignored Input
Transfer Acknowledge—If the DSP56362 is the bus master and there is
no external bus activity, or the DSP56362 is not the bus master, the TA input
is ignored. The TA input is a data transfer acknowledge (DTACK) function
that can extend an external bus cycle indefinitely. Any number of wait states
(1, 2. . .infinity) may be added to the wait states inserted by the BCR by
keeping TA deasserted. In typical operation, TA is deasserted at the start of
a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one
clock period after TA is asserted synchronous to CLKOUT. The number of
wait states is determined by the TA input or by the bus control register
(BCR), whichever is longer. The BCR can be used to set the minimum
number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the TAS bit in
the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
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