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参数资料
| 型号： | DSPB56362AG120 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 66/152页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT AUD 120MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 120MHz |
| 非易失内存： | ROM（126 kB） |
| 芯片上RAM： | 42kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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Serial Host Interface
DSP56362 Technical Data, Rev. 4
2-14
Freescale Semiconductor
2.8
Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 2-10 Serial Host Interface Signals
Signal Name
Signal Type
State during
Reset
Signal Description
SCK
SCL
Input or Output
Tri-Stated
SPI Serial Clock—The SCK signal is an output when the SPI is
configured as a master and a Schmitt-trigger input when the SPI is
configured as a slave. When the SPI is configured as a master, the
SCK signal is derived from the internal SHI clock generator. When the
SPI is configured as a slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the data transfer. The
SCK signal is ignored by the SPI if it is defined as a slave and the slave
select (SS) signal is not asserted. In both the master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled
on the opposite edge where data is stable. Edge polarity is determined
by the SPI transfer protocol.
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the
I2C mode. SCL is a Schmitt-trigger input when configured as a slave
and an open-drain output when configured as a master. SCL should
be connected to VCC through a pull-up resistor.
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
MISO
SDA
Input or Output
Input or Open-Drain
Output
Tri-Stated
SPI Master-In-Slave-Out—When the SPI is configured as a master,
MISO is the master data input line. The MISO signal is used in
conjunction with the MOSI signal for transmitting and receiving serial
data. This signal is a Schmitt-trigger input when configured for the SPI
Master mode, an output when configured for the SPI Slave mode, and
tri-stated if configured for the SPI Slave mode when SS is deasserted.
An external pull-up resistor is not required for SPI operation.
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger
input when receiving and an open-drain output when transmitting.
SDA should be connected to VCC through a pull-up resistor. SDA
carries the data for I2C transactions. The data in SDA must be stable
during the high period of SCL. The data in SDA is only allowed to
change when SCL is low. When the bus is free, SDA is high. The SDA
line is only allowed to change during the time SCL is high in the case
of start and stop events. A high-to-low transition of the SDA line while
SCL is high is a unique situation, and is defined as the start event. A
low-to-high transition of SDA while SCL is high is a unique situation
defined as the stop event.
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPB56362AG120 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSPB56362PV100 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56362PV120 | 制造商:Rochester Electronics LLC 功能描述:DIGITAL AUDIO DSP - Bulk |
| DSPB56364AF100 | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP56364 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPB56364FU100 | 制造商:Rochester Electronics LLC 功能描述:24 BIT AUDIO DSP - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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