参数资料
型号: DSPB56362AG120
厂商: Freescale Semiconductor
文件页数: 64/152页
文件大小: 0K
描述: IC DSP 24BIT AUD 120MHZ 144-LQFP
标准包装: 60
系列: DSP56K/Symphony
类型: 音频处理器
接口: 主机接口,I²C,SAI,SPI
时钟速率: 120MHz
非易失内存: ROM(126 kB)
芯片上RAM: 42kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
Host Interface (HDI08)
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
2-13
HOREQ/HORE
HTRQ/HTRQ
PB14
Output
Input, Output, or
Disconnected
GPIO Disconnected Host Request—When HDI08 is programmed to interface a
single host request host bus and the HI function is selected, this
signal is the host request (HOREQ) output. The polarity of the
host request is programmable, but is configured as active-low
(HOREQ) following reset. The host request may be programmed
as a driven or open-drain output.
Transmit Host Request—When HDI08 is programmed to
interface a double host request host bus and the HI function is
selected, this signal is the transmit host request (HTRQ) output.
The polarity of the host request is programmable, but is
configured as active-low (HTRQ) following reset. The host
request may be programmed as a driven or open-drain output.
Port B 14—When the HDI08 is configured as GPIO, this signal
is individually programmed as input, output, or internally
disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
HACK/HACK
HRRQ/HRRQ
PB15
Input
Output
Input, Output, or
Disconnected
GPIO Disconnected Host Acknowledge—When HDI08 is programmed to interface
a single host request host bus and the HI function is selected,
this signal is the host acknowledge (HACK) Schmitt-trigger input.
The polarity of the host acknowledge is programmable, but is
configured as active-low (HACK) after reset.
Receive Host Request—When HDI08 is programmed to
interface a double host request host bus and the HI function is
selected, this signal is the receive host request (HRRQ) output.
The polarity of the host request is programmable, but is
configured as active-low (HRRQ) after reset. The host request
may be programmed as a driven or open-drain output.
Port B 15—When the HDI08 is configured as GPIO, this signal
is individually programmed as input, output, or internally
disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
Table 2-9 Host Interface (continued)
Signal Name
Type
State during Reset
Signal Description
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