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参数资料
型号： DSPB56362AG120
厂商： Freescale Semiconductor
文件页数： 35/152页
文件大小： 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
标准包装： 60
系列： DSP56K/Symphony
类型： 音频处理器
接口： 主机接口，I²C，SAI，SPI
时钟速率： 120MHz
非易失内存： ROM（126 kB）
芯片上RAM： 42kB
电压 - 输入/输出： 3.30V
电压 - 核心： 3.30V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 144-LQFP
供应商设备封装： 144-LQFP（20x20）
包装： 托盘
External Memory Expansion Port (Port A)
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
2-7
BR
Output
(deasserted)
Bus Request—BR is an active-low output, never tri-stated. BR is asserted
when the DSP requests bus mastership. BR is deasserted when the DSP
no longer needs the bus. BR may be asserted or deasserted independent
of whether the DSP56362 is a bus master or a bus slave. Bus “parking”
allows BR to be deasserted even though the DSP56362 is the bus master.
(See the description of bus “parking” in the BB signal description.) The bus
request hold (BRH) bit in the BCR allows BR to be asserted under software
control even though the DSP does not need the bus. BR is typically sent to
an external bus arbitrator that controls the priority, parking, and tenure of
each master on the same external bus. BR is only affected by DSP requests
for the external bus, never for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave state.
BG
Input
Ignored Input
Bus Grant—BG is an active-low input. BG is asserted by an external bus
arbitration circuit when the DSP56362 becomes the next bus master. When
BG is asserted, the DSP56362 must wait until BB is deasserted before
taking bus mastership. When BG is deasserted, bus mastership is typically
given up at the end of the current bus cycle. This may occur in the middle of
an instruction that requires more than one external bus cycle for execution.
The default mode of operation of this signal requires a setup and hold time
referred to CLKOUT. But CLKOUT operation is not guaranteed from
100MHz and up, so the asynchronous bus arbitration must be used for clock
frequencies 100MHz and above. The asynchronous bus arbitration is
enabled by setting the ABE bit in the OMR register.
BB
Input/
Output
Input
Bus Busy—BB is a bidirectional active-low input/output. BB indicates that
the bus is active. Only after BB is deasserted can the pending bus master
become the bus master (and then assert the signal again). The bus master
may keep BB asserted after ceasing bus activity regardless of whether BR
is asserted or deasserted. This is called “bus parking” and allows the current
bus master to reuse the bus without rearbitration until another device
requires the bus. The deassertion of BB is done by an “active pull-up”
method (i.e., BB is driven high and then released and held high by an
external pull-up resistor).
The default mode of operation of this signal requires a setup and hold time
referred to CLKOUT. But CLKOUT operation is not guaranteed from
100MHz and up, so the asynchronous bus arbitration must be used for clock
frequencies 100MHz and above. The asynchronous bus arbitration is
enabled by setting the ABE bit in the OMR register.
BB requires an external pull-up resistor.
Table 2-7 External Bus Control Signals (continued)
Signal Name
Type
State during Reset
Signal Description
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