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| 型号： | GT-48001A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式以太网控制器10BaseX（10BaseX交换式快速以太网控制器） |
| 文件页数： | 25/101页 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
3
8. Unicast Intervention Mode ................................................................................................ 27
8.1
Unicast Intervention Mode Address Space ............................................................................................ 28
9. Address Table .................................................................................................................... 29
10. GalNet Messaging Protocol .............................................................................................. 31
10.1 GalNet Protocol Region ......................................................................................................................... 31
10.2 GalNet Messages Between Devices ..................................................................................................... 33
10.2.1 NEW_ADDRESS Message between GalNet devices ............................................................ 33
10.2.2 BUFFER_REQUEST Message between GalNet devices ...................................................... 34
10.2.3 START_OF_PACKET Message between GalNet devices ..................................................... 34
10.2.4 PACKET_TRANSFER Message between GalNet devices .................................................... 35
10.2.5 END_OF_PACKET Message between GalNet devices ......................................................... 35
10.3 GalNet Messages Between a GalNet Device and a CPU ...................................................................... 36
10.3.1 NEW_ADDRESS Message (GalNet to CPU) ......................................................................... 36
10.3.2 NEW_ADDRESS Message (CPU to GalNet) ......................................................................... 37
10.3.3 BUFFER_REQUEST Message (GalNet to CPU) ................................................................... 38
10.3.4 BUFFER_REQUEST Message (CPU to GalNet) ................................................................... 38
10.3.5 START_OF_PACKET Message (GalNet to CPU).................................................................. 39
10.3.6 START_OF_PACKET Message (CPU to GalNet).................................................................. 39
10.3.7 PACKET_TRANSFER Message (GalNet to CPU 16 Block Buffer)........................................ 40
10.3.8 PACKET_TRANSFER Message (GalNet to CPU in Unicast Intervention Mode)................... 41
10.3.9 PACKET_TRANSFER Message (CPU to GalNet) ................................................................. 41
10.3.10 END_OF_PACKET Message (GalNet to CPU 16 Block Buffer)............................................. 42
10.3.11 END_OF_PACKET Message (GalNet to CPU in Unicast Intervention Mode) ....................... 42
10.3.12 END_OF_PACKET Message (CPU to GalNet) ...................................................................... 43
11. PCI Bus Operation ............................................................................................................. 44
11.1 PCI Configuration Header Registers ..................................................................................................... 44
11.2 Accessing DRAM and Internal Registers through the PCI Interface ...................................................... 44
11.3 PCI Bandwidth/Performance Issues ...................................................................................................... 44
11.4 Plug-and-Play Considerations In PCI Systems ...................................................................................... 45
11.5 Unused PCI Bus in Stand-Alone Systems ............................................................................................. 45
11.6 PCI Bus Arbiter in Multiple GalNet Device Systems .............................................................................. 45
12. Ethernet Interfaces ............................................................................................................ 46
12.1 Media Access Control (MAC) ................................................................................................................ 46
12.2 Illegal Frames ........................................................................................................................................ 46
12.3 Selecting the Duplex Mode .................................................................................................................... 46
12.3.0.1 Packet Transmission .............................................................................................. 46
12.4 Backoff Algorithm Options ..................................................................................................................... 46
12.5 Manchester Encoder/Decoder ............................................................................................................... 46
12.6 Link Integrity and Auto Polarity Detector ............................................................................................... 47
12.7 Data Blinder ........................................................................................................................................... 47
12.8 Inter-Packet Gap (IPG) .......................................................................................................................... 47
12.9 Partition Mode ........................................................................................................................................ 47
12.9.1 Enabling Partition Mode ......................................................................................................... 47
12.9.2 Entering Partition State........................................................................................................... 47
12.9.3 Exiting from Partition State ..................................................................................................... 47
12.10 Back-pressure ........................................................................................................................................ 48
12.11 VLAN Tagging Support .......................................................................................................................... 48
12.12 Serial Modes .......................................................................................................................................... 48
12.12.1 Signal Polarity in Specific Serial Modes .................................................................................48
12.12.2 10BaseT Mode ....................................................................................................................... 48
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