- 您现在的位置：买卖IC网 > PDF目录67672 > GT-48001A (Galileo Technology Services, LLC) Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) PDF资料下载
参数资料
| 型号： | GT-48001A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式以太网控制器10BaseX（10BaseX交换式快速以太网控制器） |
| 文件页数： | 41/101页 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页
GT-48001A Switched Ethernet Controller
44
Revision 1.6
11.
PCI Bus Operation
The GT-48001A can act as either a master initiating a PCI bus operation, or as a target responding to a PCI bus oper-
ation. The GT-48001A is enabled to both master the PCI bus and respond to memory accesses after RESET.
The GT-48001A has two sets of internal registers that are accessible through the PCI interface. Internal control regis-
ters for the GT-48001A are memory mapped and accessible through standard PCI read/write operations. PCI control
registers are accessible through PCI configuration cycles.
11.1
PCI Configuration Header Registers
The GT-48001A’s PCI configuration registers are located in the standard PCI configuration header locations. Access to
these registers is through PCI configuration reads/writes with the IdSel signal asserted. PCI configuration registers
control PCI functions and return PCI information (device/vendor ID, etc.)
11.2
Accessing DRAM and Internal Registers through the PCI Interface
All GT-48001A internal control registers and the local DRAM are mapped into PCI memory space. The GT-48001A
looks at PCI address bits 31:22 to determine if it is the target for the current cycle. This results in a decode region of
4Mbytes per GT-48001A. Bit 21 of the address is used by the GT-48001A to subdecode on-chip between accesses to
DRAM and accesses to the internal registers. Bits 20:0 are used to select a specific register or memory location. Reg-
ister addresses given in this document refer to the value of bits 20:0 in the PCI address. The GT-48001A expects data
in little-endian format, as is required by the PCI specification.
The GT-48001A acts as a “medium speed” decide device, returning DevSel* in 2 clocks.
11.3
PCI Bandwidth/Performance Issues
The PCI bus has an ideal maximum bandwidth of just under 132Mbytes/sec (about 1 gigabit per second.) In systems
with many GalNet devices the bandwidth available on the PCI bus can become a performance limitation.
There are several factors that reduce the maximum achievable bus bandwidth:
Aggressiveness of the PCI arbiter. For example, the use of hidden arbitration can save cycles between adja-
cent access and improve overall bandwidth. Simpler arbiters will degrade bandwidth as cycles that could be
used for data transfer are used for arbitration.
The GalNet protocol does involve some overhead when compared to raw data transfer.
While performance in any given system is impossible to estimate due to design differences, Galileo Technology has
determined the theoretical maximum PCI bus loading for each 10-Mbps port (see Table 23.) The bandwidth numbers
shown in this table take into account overhead for the GalNet protocol, as well as overhead for the PCI bus itself (arbi-
tration, clocks/transfer, etc.)
Table 23 makes the following worst-case assumptions:
Packets are being received and transmitted at full wire speed (14,880 pps for 64-byte packets) in full-duplex
All ports are fully loaded
All packets must be routed across the PCI bus (not switched between ports in the same device.)
1. Maximum number of ports to guarantee 0% packet loss at worst case loading conditions.
Table 23: PCI Bandwidth Estimates
Pack et Leng th
Maximu m P CI B a ndwi d th
R e q u ir ed per 10 -Mbp s P o r t
Ma ximu m N u mb er of 10- Mbps Po rt s
per P CI B u s 1
64
2.08 Mbytes/s
63
128
1.70 Mbytes/s
78
256
1.50 Mbytes/s
88
512
1.41 Mbytes/s
94
1024
1.36 Mbytes/s
97
相关PDF资料 |
PDF描述 |
|---|---|
| GT-48002A | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| GT-48004A | Four Port Switched Fast Ethernet Controller(四端口、交换式快速以太网控制器) |
| GT-48006A | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、双端口10/100Mbps以太网桥式/交换式控制器) |
| GT-48207 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
| GT-48208 | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高级交换式 10+10/100 BaseX以太网控制器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GT482 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 82pF 3000V SL 5% (12 X 6mm) Radial 9.5mm 85°C |
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
发布紧急采购，3分钟左右您将得到回复。