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| 型号： | GT-48001A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式以太网控制器10BaseX（10BaseX交换式快速以太网控制器） |
| 文件页数： | 57/101页 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
59
HP EASE sampling requires a counter for each network segment. This counter indicates the number of packets to be
skipped before a sample is taken. When the counter reaches zero, the next packet on the network segment is captured
by the network device. Software then truncates the sampled packet, to some small fixed length, and appends a snap-
shot of specific MIB counters for that segment. The counter snapshot does not have to be taken simultaneously with
the sample. Software may introduce a delay of some milliseconds after the packet is sampled by hardware, however
minimizing this delay makes EASE more accurate. The newly created datagram is sent off to the network management
station as an SNMP trap. The network management station records the sample and counters in a database, and uses
the information to obtain traffic load estimates, top talker matrices, high-level protocol flows, and other useful sets of
information. After the sample has been taken, the CPU loads the count-down counter with the next skip count to capture
the next sampled packet. The skip count is a random value loaded by software.
EASE software in the network device must keep track of the last receive error sources and the associated error condi-
tions. The network device keeps track of errors associated with received packets and informs the CPU of the source
address (SA) of these error packets.
14.2
EASE Functionality on the GT-48001A
Support for EASE sampling is directly integrated in the GT-48001A chip, but requires the presence of a CPU in order to
function, for enabling the EASE support as well as the sample packet processing. Each GT-48001A chip supports eight
network segments (one per each port) as well as a PCI system bus. Sampling will occur only on the network segments,
and sampled packets will be sent to the CPU via the PCI system bus. Sampling is not performed on the PCI bus. It
may, however, be performed on packets received from the PCI bus, but only as a function of the counters for the desti-
nation ports (i.e. packets entering the GT-48001A via the PCI bus and being transmitted through one or more ports).
There is no counter for the PCI interface itself. Only good packets of valid length are sampled. All other packets are not
sampled and do not affect the skip count. All counters and registers implemented in the GT-48001A chip in order to
support EASE functionality, may be accessed by the CPU from the PCI system bus.
14.3
Ease_Register
A register is defined for each external port supported on the GT-48001A device. This register is used by the CPU to
load the internal count down counter, described above, with a random skip count. The count-down counter is 15 bits in
length and is used to actually determine when a sample is to be made. The GT-48001A implements a shadow register
for each of the Ease_Registers. The shadow register address is the same address as the Ease_Register address. After
a value has been written to the Ease_Register it is transferred to an internal 1 word deep FIFO (the shadow register) or
directly to the actual count-down counter if that counter is currently idle and empty. If the value can not be transferred
to the count-down counter, the value will be held in the Ease_Register shadow register until space becomes available
(i.e. a sample has been taken). If the Ease_Register shadow register was written and the CPU does attempt to write a
new value, the new value will silently replace the existing value. If the Ease_Register is empty at the time a new value
needs to be loaded into the internal counter or the shadow register, the GT-48001A will simply wait, indefinitely, for the
CPU to write a value into EASE_register. In this situation, EASE is effectively disabled on that port.
EASE (8 Registers), Offset: 0x040228 - 0x040244
14.4
EASE Interrupts
A status bit indicating the full/empty status of the Ease_Register for each external port supported on the GT-48001A, is
maintained as part of the Interrupt Cause register. When a value is moved from the Ease_Register into an internal
counter or shadow register, a bit is reset in the Interrupt Cause register indicating that the Ease_Register is now empty.
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
14:0
Ease_Register
value loaded to the internal count-down counter of port 0
0x0
31:15
-
Reserved.
-
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