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参数资料
| 型号： | GT-48001A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式以太网控制器10BaseX（10BaseX交换式快速以太网控制器） |
| 文件页数： | 84/101页 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
Revision 1.6
83
Port MIB Counters (8 Blocks), Offset: 0x040000 - 0x0401 fc
The CPU must read all of the MIB counters during initialization in order to reset the counters to ‘0’. All counters are 32-
bits. The counters will only be reset to ‘0’ if MIBClrMode (bit 30 of the Global Control Register) is set to ‘0’ (default). If
MIBClrMode bit is ‘1’, reading the MIB counters will have no effect. The CPU must access the counters using single
datum transactions (burst reads/writes are not allowed.)
Table 37 lists definitions for terms used in the counter descriptions.
Table 37: Definitions Used in Counter Descriptions
Te rm
De fin i t i on
Packet Data Section
All data bytes in the packet following the SFD until the end of the packet
Packet Data Length
The number of data bytes in the packet data section
Data Octet
A single byte from the packet data section
Received Good
Packet
A received packet which is not rejected and enters the switching core to be trans-
mitted later
Received Good Uni-
cast Packet
A received packet which is not rejected and enters the switching core to be trans-
mitted later, with destination address which is a unicast address
Received Good Multi-
cast Packet
A received packet which is not rejected and enters the switching core to be trans-
mitted later, with destination address which is a multicast address
Received Good
Broadcast Packet
A received packet which is not rejected and enters the switching core to be trans-
mitted later, with destination address which is a broadcast address
Transmitted Good
Packet
Any transmitted packet from the GT-48001A
Dropped Packet
A received packet which is ignored due to lack of available receive buffers (port is
in buffer_full state)
Local Packet
A received packet whose destination address is mapped to the receiving port
Rejected Packet
A received packet which is not forwarded due to error such as bad CRC, Rx Error
Event, Invalid size (too short or too long).
MIBCtrMode
Bit 26, MIBCtrMode, of the Global Control Register (offset 0x140028)
VTagEn
Bit 13, VTagEn, of the Port Control Register (offset 0x040200-0x04021c)
MAXFRAMESIZE
1518 for VTagEn = 0 (default) or 1522 for VTagEn = 1
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