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| 型号： | GT-48001A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式以太网控制器10BaseX（10BaseX交换式快速以太网控制器） |
| 文件页数： | 50/101页 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
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GT-48001A Switched Ethernet Controller
52
Revision 1.6
12.12.4
AUI Mode
12.12.4.1 TxD Pins
When the GT-48001A is in AUI mode, the default value of TxD pins in an idle state (i.e. when the GT-48001A is not
transmitting) is ‘1’. The default value of the TxD pins of the GT-48001 in a idle state is ‘0’.
12.12.4.2 AUILinkUp
In AUI mode, The AUILinkUp[7:0] pins of the GT-48001A are used as inputs to indicate the link status which can be
driven by the PHY. When the respective AUILinkUp[7:0] pin is a ‘1’, the port has established link. When the respective
AUILinkUp[7:0] pin is a ‘0’, the link has failed on that port. The port will enter a link-test-fail state in which it performs
similarly to a 10BaseT port in the link-test-fail state. This includes:
1.
the port will ignore incoming packets
2.
the port will not transmit packets
3.
packets will not be forwarded to the port from the PCI nor other ports on the same GT-48001A
4.
the LED interface will indicate link-test-fail state for the port
5.
since the transmission are halted, the MIB counters for the port will reflect the true wire activity
12.12.4.3 Setting DAddr[6] on Reset
A: The IEEE Ethernet Spec defines the beginning of the interframe-gap after both transmission and carrier-sense have
stopped. To comply with the Ethernet MAC specification, the GT-48001 and GT-48001A, start measuring the inter-
frame-gap after both transmission and carrier-sense have stopped. The external tranceiver loopback function (loop
back of TxD transmission back to the RxD input), defines the period of time from the end of GT-48001/GT-48001A
transmission, and the end of the carrier-sense (which is deasserted following the end of loop-back on RxD). Effectively,
the interframe-gap is increased relative to the programmed/default value IPG due to the loop-back. This prevents the
GT-48001A from meeting full-wire speed transmissions, unless DAddr[6] is LOW. When DAddr[6] is LOW, the inter-
packet gap will restart at the end of TxEn, ignoring any loopback of TxD back to RxD. This will enable the GT-48001A
port to meet full-wire speed transmissions. When DAddr[6] is HIGH the inter-packet gap will restart when there is no
transmit or receive activity (GT-48001 compatible).
Table 29: AUI Interface Pin Descriptions
Pi n Na m e
I/ O
AUI Mod e
Fu n c t i on a l it y
SClk
I
80 MHz
80 MHz Clock.
RxD
I
RxD
Receive Data: Manchester encoded data.
RxLP
I
Coll
Collision Detect: Active HIGH. A collision is indicated by the
CSO signal (10 MHz signal).
CrS
O
CrS
Carrier Sense: Indicates presence on received packet (pre-
amble to SOI).
Pol[0]
I
AUILinkUp[0]
This pin carries the link status driven from the external PHY.
Pol[7:1]
I
AUILinkUp[7:1]
These pins carries the link status driven from the external
PHY.
TxD
O
TxD
Transmit Data.
TxDDel
O
NC
Do not drive this pin.
TxEn
O
TxEn
Transmit Enable: Indicates that the data is present on TxD
and TxD_DL lines.
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